CMOS device

• US 7,022,561 B2
• Filed: 12/02/2002
• Issued: 04/04/2006
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hu, Chenming, Huang, Chien-Chao, Ge, Chung-Hu, Wang, Chao-Hsing
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/307,619
• Publication Number:
  US 20040104405A1
• Time in Patent Office: 1,219 Days
• Field of Search: 438/189, 438786-788, 438/791, 438/792, 438/197, 438/199
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

Claims

1. A method, comprising:

providing a substrate having an NMOS device adjacent a PMOS device;

forming a first stress layer over the NMOS and PMOS devices, the first stress layer comprising one of a first tensile-stress layer and a compression-stress layer;

forming an etch stop layer over the first stress layer;

removing the first stress layer and the etch stop layer from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device;

forming a second tensile-stress layer over the NMOS device and over the first stress layer and the etch stop layer over the PMOS device; and

removing the second tensile-stress layer and the etch stop layer from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

2. The method of claim 1 wherein the substrate comprises silicon-germanium.

3. The method of claim 1 wherein at least one of the first stress layer and the second tensile-stress layer comprises SiON.

4. The method of claim 1 wherein:

the one is the first tensile-stress layer;

forming the first stress layer includes forming the first stress layer by rapid thermal chemical-vapor deposition (RTCVD) processing; and

forming the second tensile-stress layer includes forming the second tensile-stress layer by rapid thermal chemical-vapor deposition (RTCVD) processing.

5. The method of claim 4 wherein process parameters of the RTCVD processing include a temperature ranging between about 400°

C. and about 700°

C., a time period ranging between about 20 seconds and about 120 seconds, and a pressure ranging between about 10 Torr and about 400 Torr.

6. The method of claim 1 wherein:

the one is the compression-stress layer;

forming the first stress layer includes forming the first stress layer by plasma-enhanced chemical-vapor deposition (PECVD) processing; and

forming the second tensile-stress layer includes forming the second tensile-stress layer by rapid thermal chemical-vapor deposition (RTCVD) processing.

7. The method of claim 6 wherein process parameters of the RTCVD processing include a temperature ranging between about 400°

C. and about 700°

C., a time period ranging between about 20 seconds and about 120 seconds, and a pressure ranging between about 10 Torr and about 400 Torr.

8. The method of claim 7 wherein process parameters of the PECVD processing include a temperature ranging between about 300°

C. and about 600°

C., a time period ranging between about 20 seconds and about 120 seconds, and a pressure ranging between about 1.0 Torr and about 1.5 Torr.

9. The method of claim 8 wherein the RTCVD process parameters include an NH3:

Si4 gas ratio ranging between about 50;

1 and about 400;

1 and the PECVD process parameters include an NH3;

SiH4 gas ratio ranging between about 4;

1 and about 10;

1

10. The method of claim 1 wherein:

removing the first stress layer from over the NMOS device includes forming a patterning layer over the PMOS device and not over the NMOS device; and

removing the second tensile-stress layer from over the PMOS device includes forming a patterning layer over the NMOS device and not over the PMOS device.

11. The method of claim 1 wherein at least one of the first stress layer and the second tensile-stress layer comprises silicon oxynitride.

12. The method of claim 1 wherein:

forming the first stress layer includes forming the first stress layer by plasma-enhanced chemical-vapor deposition (PECVD) processing.

13. The method of claim 1 wherein:

forming the second tensile-stress layer includes forming the second tensile-stress layer by rapid thermal chemical-vapor deposition (RTCVD) processing.

14. A method, comprising:

forming a first stress layer over at least one of an NMOS device and a PMOS device each located in a substrate, the first stress layer comprising one of a first tensile-stress layer and a compression-stress layer;

forming an etch stop layer over at least a portion of the first stress layer;

removing at least a portion of the first stress layer and the etch stop layer from over at least the NMOS device, leaving at least a portion of the first stress layer and at least a portion of the etch stop layer over at least a substantial portion of the PMOS device;

forming a second stress layer over at least one of the NMOS device and the first stress layer, the second stress layer comprising a second tensile-stress layer; and

removing at least a portion of the second stress layer from over at least the PMOS device, leaving at least a portion of the second stress layer over at least a substantial portion of the NMOS device.

15. The method of claim 14 wherein the NMOS device is one of a plurality of NMOS devices each located in the substrate and the PMOS device is one of a plurality of PMOS devices each located in the substrate.

16. The method of claim 14 wherein the substrate comprises silicon-germanium.

17. The method of claim 14 wherein the first stress layer and the second stress layer each comprise silicon nitride.

18. The method of claim 14 wherein the first stress layer and the second stress layer each comprise silicon oxynitride.

19. The method of claim 14 wherein forming the first stress layer includes rapid thermal chemical-vapor deposition (RTCVD) processing.

20. The method of claim 14 wherein forming the second stress layer includes rapid thermal chemical-vapor deposition (RTCVD) processing.

21. The method of claim 14 wherein forming the second stress layer includes plasma-enhanced chemical-vapor deposition (PECVD) processing.

22. The method of claim 14 wherein forming the first stress layer includes rapid thermal chemical-vapor deposition (RTCVD) processing and forming the second stress layer includes plasma-enhanced chemical-vapor deposition (PECVD) processing.

23. The method of claim 14 wherein forming the first stress layer includes rapid thermal chemical-vapor deposition (RTCVD) processing and forming the second stress layer includes RTCVD processing.

24. The method of claim 14 wherein the one of the first tensile-stress layer and the compression-stress layer is the compression-stress layer.

25. The method of claim 24 wherein the first stress layer and the second stress layer each comprise one of silicon nitride and silicon oxynitride.

26. The method of claim 24 wherein forming the first stress layer includes rapid thermal chemical-vapor deposition (RTCVD) processing and forming the second stress layer includes plasma-enhanced chemical-vapor deposition (PECVD) processing.

27. The method of claim 14 wherein the one of the first tensile-stress layer and the compression-stress layer is the first tensile-stress layer.

28. The method of claim 27 wherein the first stress layer and the second stress layer each comprise one of silicon nitride and silicon oxynitride.

29. The method of claim 27 wherein forming the first stress layer includes rapid thermal chemical-vapor deposition (RTCVD) processing and forming the second stress layer includes RTCVD processing.

30. The method of claim 14 wherein forming the second stress layer includes forming the second stress layer over at least a portion of the NMOS device, at least a portion of the first stress layer, and at least a portion of the etch stop layer over the PMOS device, and wherein removing at least a portion the second stress layer includes removing at least a portion of the etch stop layer.