Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells

• US 7,022,572 B2
• Filed: 11/19/2004
• Issued: 04/04/2006
• Est. Priority Date: 03/31/2003
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Knall, N. Johan
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/994,020
• Publication Number:
  US 20050101088A1
• Time in Patent Office: 501 Days
• Field of Search: 438/131, 438/200, 438/257, 438/333, 438/467, 438/600, 365/185.02, 365/185.18
• US Class Current: 438/257
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode

Abstract

In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.

Claims

1. A method for manufacturing an integrated circuit memory device comprising:

providing a programmable memory array of passive element memory cells, each memory cell comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of X-lines, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of Y-lines, said first semiconductor region being more lightly doped than the second semiconductor region; and

providing array support circuitry configured for impressing a programming pulse on a selected X-line and a programming pulse on a first selected Y-line;

wherein the selected X-line is pulsed from an unselected X-line bias voltage to a selected X-line bias voltage, and the first selected Y-line is pulsed from an unselected Y-line bias voltage to a selected Y-line bias voltage; and

wherein the first selected Y-line pulse substantially falls within the selected X-line pulse.

2. The method of claim 1 wherein the programmable memory array comprises antifuse memory cells.

3. The method of claim 1 wherein the selected X-line pulse and the first selected Y-line pulse are timed so that a selected memory cell, once programmed, is reversed biased whenever the first selected X-line voltage is more than 10% toward the unselected X-line bias voltage relative to the selected X-line bias voltage.

4. The method of claim 1 wherein the memory array comprises a three-dimensional array having at least three array line layers defining at least two memory planes.

5. The method of claim 4 wherein the memory array comprises memory cells whose first semiconductor region is alternately an upper region of some memory planes and a lower region of vertically adjacent memory planes.

6. The method of claim 4 wherein the memory array comprises memory cells whose first semiconductor region is either an upper region of all memory planes, or a lower region of all memory planes.

7. The method of claim 1 wherein each respective X-line comprises a semiconductor layer coupled between the respective first semiconductor regions of adjacent memory cells associated with the respective X-line.

8. The method of claim 1 wherein the array comprises at least one layer of rail-stack array lines.

9. The method of claim 8 wherein at least one layer of passive element memory cell material is continuous along the selected X-line.

10. The method of claim 8 wherein each respective X-line comprises a continuous semiconductor layer that forms the respective first semiconductor region of memory cells associated therewith.

11. The method of claim 8 wherein each respective X-line comprises a continuous semiconductor layer that connects to the respective first semiconductor region of memory cells associated therewith, wherein the continuous semiconductor layer and the respective first semiconductor regions have a different doping density.

12. The method of claim 8 wherein each X-line comprises a rail-stack.

13. The method of claim 1 wherein the selected X-line pulse and the first selected Y-line pulse are timed so that the first selected Y-line transitions at least a first percentage toward the unselected Y-line bias voltage before the selected X-line transitions at most a second percentage toward the unselected X-line bias voltage.

14. The method of claim 13 wherein:

the first percentage comprises around 50%; and

the second percentage comprises around 50%.

15. The method of claim 13 wherein:

the first percentage comprises around 90%; and

the second percentage comprises around 10%.

16. The method of claim 13 wherein the selected X-line pulse and the first selected Y-line pulse are timed so that the selected X-line transitions at least a third percentage toward the selected X-line bias voltage before the first selected Y-line transitions at most a fourth percentage toward the selected Y-line bias voltage.

17. The method of claim 16 wherein:

the third percentage comprises around 50%; and

the fourth percentage comprises around 50%.

18. The method of claim 16 wherein:

the third percentage comprises around 90%; and

the fourth percentage comprises around 10%.

19. The method of claim 1 wherein:

the first semiconductor region of each memory cell comprises a p−

region.

20. The method of claim 1 wherein:

the first semiconductor region of each memory cell comprises an n−

region;

the second semiconductor region of each memory cell comprises a p+region;

the selected X-line is pulsed with a negative-going programming pulse; and

the first selected Y-line is pulsed with a positive-going programming pulse.

21. The method of claim 1 further comprising programming more than one memory cell associated with a selected X-line line by pulsing each of at least two Y-lines substantially within a single X-line pulse.

22. The method of claim 1 further comprising:

pulsing a second selected Y-line coupled to a second selected memory cell from the unselected Y-line bias voltage to the selected Y-line bias voltage, said second selected memory cell also being coupled to the first selected X-line;

wherein the second selected Y-line pulse substantially occurs within the selected X-line pulse.

23. The method of claim 22 wherein the first selected Y-line pulse and the second selected Y-line pulse substantially overlap.

24. The method of claim 22 wherein the first selected Y-line pulse and the second selected Y-line pulse do not substantially overlap.

25. The method of claim 22 wherein:

the memory array comprises a three-dimensional array having at least two memory planes; and

the first selected memory cell and the second selected memory cell fall within different memory planes.