Capacitive resonators and methods of fabrication

• US 7,023,065 B2
• Filed: 07/31/2003
• Issued: 04/04/2006
• Est. Priority Date: 08/07/2002
• Status: Expired due to Term

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Ayazi, Farrokh, Anaraki, Siavash Pourkamali
• Primary Examiner(s): Kang, Donghee
• Application Number:
  US10/632,176
• Publication Number:
  US 20040065940A1
• Time in Patent Office: 978 Days
• Field of Search: 257414-417, 257/622, 438/22, 438/50, 438/52, 438/53, 338186-192, 307/110
• US Class Current: 257/414
• CPC Class Codes: H03H 2009/02496 Horizontal, i.e. parallel to the substrate plane
• CPC Class Codes: H03H 2009/02503 Breath-like, e.g. Lam? mode, wine-glass mode
• CPC Class Codes: H03H 3/0072 of microelectro-mechanical resonators or networks micromembranes or microbeams B81B2203/01; manufacture of microstructural devices in general B81C
• CPC Class Codes: H03H 9/2463 Clamped-clamped beam resonators

Abstract

A micro-electro-mechanical system (MEMS) capacitive resonator and methods for manufacturing the same are invented and disclosed. In one embodiment, a method comprises forming trenches in a substrate, conformally coating the substrate with an oxide, filling the coated trenches with polysilicon, patterning the polysilicon, releasing a resonating structure derived from the substrate, and removing the conformally coated oxide.

Claims

1. A method for fabricating micro-electro-mechanical system (MEMS) capacitive resonators, the method comprising:

forming trenches in a semiconductor-on-insulator substrate;

conformally coating sidewalls of the trenches with an oxide;

filling the coated trenches with polysilicon, wherein electrodes are derived from the polysilicon;

forming release openings and removing the polysilicon and at least a portion of the semiconductor-on-silicon substrate; and

removing the conformally coated oxide and an oxide of the semiconductor-on-insulator substrate, wherein a capacitive gap is formed, wherein a resonating element of one of the capacitive resonators is released.

2. The method of claim 1, further including:

growing and patterning an insulator oxide, wherein the insulator oxide provides isolation between the semiconductor-on-insulator substrate and wire-bonding pads;

depositing and patterning nitride, wherein the nitride provides protection for the insulator oxide disposed on the pads;

growing and removing a surface treatment oxide, wherein the surface treatment oxide enables the reduction of the roughness of sidewalls of the resonating element;

depositing polysilicon to form the wirebonding pads for drive and sense electrodes;

metallizing the pads; and

wherein removing the polysilicon includes patterning the polysilicon inside the trenches.

3. The method of claim 1, wherein the forming release openings comprises anisotropically etching to an oxide layer of the semiconductor-on-insulator substrate, such that the undercut of the resonating element is facilitated.

4. The method of claim 1, wherein the filling includes one of filling the trenches with doped LPCVD polysilicon such that the electrodes are formed vertically and depositing and patterning doped LPCVD polysilicon.

5. The method of claim 1, wherein the forming trenches includes one of deep reactive ion etching and regular reactive ion etching to an oxide layer of the semiconductor-on-insulator substrate.

6. The method of claim 1, wherein the conformally coating includes depositing a LPCVD high-temperature oxide of approximately less than 100 nanometers.

7. The method of claim 1, wherein the conformally coating is scalable to correspond to a desired thickness of a lateral gap spacing for the capacitive resonator.

8. The method of claim 1, wherein the removing comprises an anisotropic plasma etching such that at least a portion of the oxide remains on sidewalls of the resonating element.

9. The method of claim 1, wherein the releasing comprises exposing the semiconductor-on-insulator substrate to a solution comprising HF:

H20 to release the resonating element from a handle layer and the electrodes.

10. The method of claim 1, wherein the forming trenches includes etching high-aspect ratio trenches.

11. The method of claim 1, wherein the removing includes forming a gap between the resonating element and the polysilicon in a self-aligned manner.

12. The method of claim 1, wherein the removing is performed to form a plurality of capacitive gaps and release a plurality of resonating elements, each of the plurality of resonating elements electrically isolated from each other.

13. The method of claim 1, further including conformally coating surfaces of the semiconductor-on-insulator substrate with the oxide associated with conformal coating.

14. A method for fabricating micro-electro-mechanical system (MEMS) capacitive resonators, the method comprising:

forming trenches in a semiconductor-on-insulator substrate;

conformally coating the sidewalls of the trenches with an oxide;

filling the coated trenches with polysilicon, wherein electrodes are derived from the polysilicon;

forming release openings and removing the polysilicon and at least a portion of the semiconductor-on-silicon substrate without isotropic etching of the polysilicon or semiconductor portion of the semiconductor-on-silicon substrate; and

removing the conformally coated oxide and an oxide of the semiconductor-on-insulator substrate, wherein a capacitive gap is formed, wherein a resonating element of one of the capacitive resonators is released.

15. The method of claim 14, further including:

growing and patterning an insulator oxide, wherein the insulator oxide provides isolation between the semiconductor-on-insulator substrate and wire-bonding pads;

depositing and patterning nitride, wherein the nitride provides protection for the insulator oxide disposed on the pads;

growing and removing a surface treatment oxide, wherein the surface treatment oxide enables the reduction of the roughness of sidewalls of the resonating element;

depositing polysilicon to form the wirebonding pads for drive and sense electrodes;

metallizing the pads; and

wherein removing the polysilicon includes patterning the polysilicon inside the trenches.

16. The method of claim 14, wherein the forming release openings comprises anisotropically etching to an oxide layer of the semiconductor-on-insulator substrate;

such that the undercut of the resonating element is facilitated.

17. The method of claim 14, wherein the filling includes one of filling the trenches with doped LPCVD polysilicon such that the electrodes are formed vertically and depositing and patterning doped LPCVD polysilicon.

18. The method of claim 14, wherein the forming trenches includes one of deep reactive ion etching and regular reactive ion etching to an oxide layer of the semiconductor-on-insulator substrate.

19. The method of claim 14, wherein the conformally coating includes depositing a LPCVD high-temperature oxide of approximately less than 100 nanometers.

20. The method of claim 14, wherein the conformally coating is scalable to correspond to a desired thickness of a lateral gap spacing for the capacitive resonator.

21. The method of claim 14, wherein the removing comprises an anisotropic plasma etching such that at least a portion of the oxide remains on sidewalls of the resonating element.

22. The method of claim 14, wherein the releasing comprises exposing the semiconductor-on-insulator substrate to a solution comprising HF:

H20 to release the resonating element from a handle layer and the electrodes.

23. The method of claim 14, wherein the forming trenches includes etching high-aspect ratio trenches.

24. The method of claim 14, further including conformally coating surfaces of the semiconductor-on-insulator substrate with the oxide associated with conformal coating.

25. A method for fabricating micro-electro-mechanical system (MEMS) capacitive resonators having sharply defined boundaries, the method consisting of:

growing or depositing an oxide layer on a semiconductor-on-insulator substrate and patterning the oxide to the shape of the resonators;

forming trenches in the semiconductor-on-insulator substrate by using the oxide layer as a mask;

conformally coating sidewalls of the trenches with an oxide;

filling the coated trenches with polysilicon, wherein electrodes are derived from the polysilicon;

forming release openings and removing the polysilicon and at least a portion of the semiconductor-on-silicon substrate without isotropic etching of the polysilicon or semiconductor portion of the semiconductor-on-silicon substrate; and

forming a resonating element having sharply defined boundaries of one of the capacitive resonators by removing the conformally coated oxide and an oxide of the semiconductor-on-insulator substrate, wherein a capacitive gap is formed, wherein the resonating element is released.

26. A method for fabricating micro-electro-mechanical system (MEMS) capacitive resonators having a height-to-width ratio of less than one, the method comprising:

forming trenches in a semiconductor-on-insulator substrate;

conformally coating sidewalls of the trenches with an oxide;

filling the coated trenches with polysilicon, wherein electrodes are derived from the polysilicon;

forming release openings and removing the polysilicon and at least a portion of the semiconductor-on-silicon substrate without isotropic etching of the polysilicon or semiconductor portion of the semiconductor-on-silicon substrate; and

forming a resonating element having a height-to-width ratio of less than one of the capacitive resonators by removing the conformally coated oxide and an oxide of the semiconductor-on-insulator substrate, wherein a capacitive gap is formed, wherein the resonating element is released.

27. The method of claim 26, further including:

growing and patterning an insulator oxide, wherein the insulator oxide provides isolation between the semiconductor-on-insulator substrate and wire-bonding pads;

depositing and patterning nitride, wherein the nitride provides protection for the insulator oxide disposed on the pads;

growing and removing a surface treatment oxide, wherein the surface treatment oxide enables the reduction of the roughness of sidewalls of the resonating element;

depositing polysilicon to form the wirebonding pads for drive and sense electrodes;

metallizing the pads; and

wherein removing the polysilicon includes patterning the polysilicon inside the trenches.

28. The method of claim 26, wherein the forming release openings comprises anisotropically etching to an oxide layer of the semiconductor-on-substrate, such that the undercut of the resonating element is facilitated.

29. The method of claim 26, wherein the filling includes one of filling the trenches with doped LPCVD polysilicon such that the electrodes are formed vertically and depositing and patterning doped LPCVD polysilicon.

30. The method of claim 26, wherein the forming trenches includes one of deep reactive ion etching and regular reactive ion etching to an oxide layer of the semiconductor-on-insulator substrate.

31. The method of claim 26, wherein the conformally coating includes depositing a LPCVD high-temperature oxide of approximately less than 100 nanometers.

32. The method of claim 26, wherein the conformally coating is scalable to correspond to a desired thickness of a lateral gap spacing for the capacitive resonator.

33. The method of claim 26, wherein the removing comprises an anisotropic plasma etching such that at least a portion of the oxide remains on sidewalls of the resonating element.

34. The method of claim 26, wherein the releasing comprises exposing the semiconductor-on-insulator substrate to a solution comprising HF:

H20 to release the resonating element from a handle layer and the electrodes.

35. the method of claim 26, further comprising conformally coating surfaces of the semiconductor-on-insulator substrate with the oxide associated with conformal coating.