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Bonding pad and via structure design

  • US 7,023,090 B2
  • Filed: 01/29/2003
  • Issued: 04/04/2006
  • Est. Priority Date: 01/29/2003
  • Status: Active Grant
First Claim
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1. A bonding pad design, comprising:

  • a semiconductor substrate;

    a first dielectric layer over the semiconductor substrate;

    at least first and second interlocked conductive pads formed within the first dielectric layer, the first and second conductive pads being electrically isolated from each other;

    a second dielectric layer over the first dielectric layer; and

    at least first and second bonding pads formed in the second dielectric layer, the first and second bonding pads being electrically isolated from each other, and wherein the first conductive pad is electrically coupled to the first bonding pad and the second conductive pad is electrically coupled to the second bonding pad.

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