High voltage tolerant power up detector

• US 7,023,248 B2
• Filed: 05/27/2004
• Issued: 04/04/2006
• Est. Priority Date: 05/27/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ott, Patrick J.
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US10/856,261
• Publication Number:
  US 20050264329A1
• Time in Patent Office: 677 Days
• Field of Search: 327/142, 327/143, 327/198
• US Class Current: 327/143
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A high voltage tolerant (“HVT”) power up detector. The HVT power up detector includes a voltage detector circuit coupled to a high voltage tolerant transistor (“HVTT”). The voltage detector circuit determines when a voltage supply is above a threshold logic level voltage. The HVTT has a gate coupled to receive a logic level voltage and a source and a drain to couple between the voltage supply and the voltage detector circuit. The HVTT shelters the voltage detector circuit from voltages above the logic level voltage when the voltage supply exceeds the logic level voltage.

Claims

1. An apparatus, comprising:

a voltage detector circuit coupled to determine when a voltage supply is above a threshold logic level voltage; and

a high voltage tolerant transistor (“

HVTT”

) having a gate coupled to receive a logic level voltage and a source and a drain to couple between the voltage supply and the voltage detector circuit, the HVTT to shelter the voltage detector circuit from voltages above the logic level voltage when the voltage supply exceeds the logic level voltage, wherein the HVTT comprises a lightly doped drain negative metal oxide semiconductor (“

LDDNMOS”

) transistor.

2. The apparatus of claim 1, wherein the HVTT is configured to shelter the voltage detector circuit from voltage levels high enough to damage the voltage detector circuit.

3. The apparatus of claim 2, wherein the source of the LDDNMOS transistor is coupled to the voltage detector circuit and the drain of the LDDNMOS transistor is to couple to the voltage supply.

4. The apparatus of claim 1, wherein the voltage detector circuit comprises:

a first current path including a first resistive element and a first transistor coupled in series;

a second current path including a second transistor and a second resistive element coupled in series, the first current path and the second current path coupled in parallel between the HVTT and a ground path; and

a voltage comparator having first and second inputs, the first input coupled to a first node between the first transistor and the first resistive element and the second input coupled to a second node between the second transistor and the second resistive element, the comparator to compare a first voltage of the first node against a second voltage of the second node.

5. The apparatus of claim 4, wherein the first transistor comprises an NMOS transistor having a drain and a gate coupled together.

6. The apparatus of claim 5, wherein the second transistor comprises a positive MOS (“

PMOS”

) transistor having a gate coupled to the ground path.

7. The apparatus of claim 4, wherein the first and second resistive elements have resistances selected such that the first node and the second node have substantially equivalent voltages when the voltage supply provides a voltage approximately equal to the threshold logic level voltage.

8. The apparatus of claim 1, wherein the voltage detector circuit further comprises an output to enable low voltage logic when the voltage supply is above the threshold logic level voltage.

9. A method, comprising:

powering on a logic voltage supply coupled to low voltage logic, the logic voltage supply to generate a first supply voltage;

powering on a high voltage supply coupled to high voltage circuitry, the high voltage supply to generate a second supply voltage high enough to damage the low voltage logic, wherein the high voltage circuitry includes fusible read only memory(“

ROM”

);

generating an enable signal with a high voltage tolerant (“

HVT”

) power up detector when the first supply voltage and the second supply voltage both exceed a threshold logic voltage level, the enable signal to enable operation of the low voltage logic; and

writing to the fusible ROM using the second supply voltage generated by the high voltage supply.

10. The method of claim 9, further comprising sheltering voltage detector components of the HVT power up detector not capable of tolerating the second supply voltage from a portion of the second supply voltage exceeding the first supply voltage using a high voltage tolerant transistor (“

HVTT”

) coupled between the voltage detector components and the high voltage supply.

11. The method of claim 10, wherein the low voltage logic includes control logic to control the writing to the fusible ROM.

12. The method of claim 10, wherein generating the enable signal when the first supply voltage and the second supply voltage both exceed the threshold logic voltage level comprises:

driving a gate of the HVTT with the logic voltage supply;

driving a drain of the HVTT with the high voltage supply;

driving source current of the HVTT through a first current path and a second current path coupled in parallel between a source of the HVTT and a ground path, the first current path including a first resistive element and a first transistor coupled in series, the second current path including a second transistor and a second resistive element coupled in series; and

comparing a first voltage generated at a first node between the first resistive element and the first transistor against a second voltage generated at a second node between the second transistor and the second resistive element.

13. A machine-accessible medium having contained thereon a description of an integrated circuit, the integrated circuit comprising:

a voltage detector circuit coupled to determine when a voltage supply is above a threshold logic level voltage; and

a high voltage tolerant transistor (“

HVTT”

) having a gate coupled to receive a logic level voltage and a source and a drain coupled between a power rail and the voltage detector circuit, the HVTT to shelter the voltage detector circuit from voltages on the power rail above the logic level voltage, wherein the voltage detector includes;

a first current path including a first resistive element and a first transistor coupled in series;

a second current path including a second transistor and a second resistive element coupled in series, the first current path and the second current path coupled in parallel between the HVTT and a ground path; and

a voltage comparator having first and second inputs, the first input coupled to a first node between the first transistor and the first resistive element and the second input coupled to a second node between the second transistor and the second resistive element, the comparator to compare a first voltage of the first node against a second voltage of the second node.

14. The machine-accessible medium of claim 13, wherein the HVTT comprises a lightly doped drain negative metal oxide semiconductor (“

LDDNMOS”

) transistor and wherein the source is coupled to the voltage detector circuit and the drain is to couple to the power rail.

15. The machine-accessible medium of claim 13, wherein the power rail comprises a dual voltage power rail to switchably couple to a high voltage supply and a logic voltage supply.

16. An integrated circuit, comprising:

low voltage logic coupled to a first power rail and operable above a threshold logic level voltage, the first power rail to couple to a logic voltage supply to receive a logic level voltage;

high voltage circuitry coupled to a second power rail and operable at a high level voltage, the second power rail to couple to a high voltage supply to receive the high level voltage, wherein the second power rail comprises a dual voltage power rail to switchably couple to both the high voltage supply and the logic voltage supply, the high level voltage above the logic level voltage and detrimental to the low voltage logic; and

a high voltage tolerant (“

HVT”

) power up detector coupled to the first power rail and to the second power rail, the HVT power up detector to enable the low voltage logic when the first power rail is above a threshold logic level voltage, HVT power up detector to receive the high level voltage without detriment.

17. The integrated circuit of claim 16, wherein the HVT power up detector is further coupled to enable the high voltage circuitry when the logic voltage supply is above the threshold logic level voltage.

18. The integrated circuit of claim 17, wherein the high voltage circuitry comprises fusible read only memory (“

ROM”

) writable at the high level voltage and readable at the logic level voltage.

19. The integrated circuit of claim 16, wherein the HVT power up detector comprises:

a voltage detector circuit to generate an output to enable the low voltage logic; and

a high voltage tolerant transistor (“

HVTT”

) having a gate coupled to the first power rail and a source and a drain to couple between the second power rail the voltage detector circuit, the HVTT to shelter the voltage detector circuit from voltages above the logic level voltage.

20. The integrated circuit of claim 19, wherein the HVTT comprises a lightly doped drain negative metal oxide semiconductor (“

LDDNMOS”

) transistor and wherein the source is coupled to the voltage detector circuit and the drain is to couple to the second power rail.

21. The integrated circuit of claim 20, wherein the voltage detector comprises

a first current path including a first resistive element and a first transistor coupled in series;

a second current path including a second transistor and a second resistive element coupled in series, the first current path and the second current path coupled in parallel between the HVTT and a ground path; and

a voltage comparator having first and second inputs, the first input coupled to a first node between the first transistor and the first resistive element and the second input coupled to a second node between the second transistor and the second resistive element, the comparator to compare a first voltage of the first node against a second voltage of the second node.