High voltage tolerant power up detector
First Claim
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1. An apparatus, comprising:
- a voltage detector circuit coupled to determine when a voltage supply is above a threshold logic level voltage; and
a high voltage tolerant transistor (“
HVTT”
) having a gate coupled to receive a logic level voltage and a source and a drain to couple between the voltage supply and the voltage detector circuit, the HVTT to shelter the voltage detector circuit from voltages above the logic level voltage when the voltage supply exceeds the logic level voltage, wherein the HVTT comprises a lightly doped drain negative metal oxide semiconductor (“
LDDNMOS”
) transistor.
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Abstract
A high voltage tolerant (“HVT”) power up detector. The HVT power up detector includes a voltage detector circuit coupled to a high voltage tolerant transistor (“HVTT”). The voltage detector circuit determines when a voltage supply is above a threshold logic level voltage. The HVTT has a gate coupled to receive a logic level voltage and a source and a drain to couple between the voltage supply and the voltage detector circuit. The HVTT shelters the voltage detector circuit from voltages above the logic level voltage when the voltage supply exceeds the logic level voltage.
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Citations
21 Claims
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1. An apparatus, comprising:
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a voltage detector circuit coupled to determine when a voltage supply is above a threshold logic level voltage; and a high voltage tolerant transistor (“
HVTT”
) having a gate coupled to receive a logic level voltage and a source and a drain to couple between the voltage supply and the voltage detector circuit, the HVTT to shelter the voltage detector circuit from voltages above the logic level voltage when the voltage supply exceeds the logic level voltage, wherein the HVTT comprises a lightly doped drain negative metal oxide semiconductor (“
LDDNMOS”
) transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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powering on a logic voltage supply coupled to low voltage logic, the logic voltage supply to generate a first supply voltage; powering on a high voltage supply coupled to high voltage circuitry, the high voltage supply to generate a second supply voltage high enough to damage the low voltage logic, wherein the high voltage circuitry includes fusible read only memory(“
ROM”
);generating an enable signal with a high voltage tolerant (“
HVT”
) power up detector when the first supply voltage and the second supply voltage both exceed a threshold logic voltage level, the enable signal to enable operation of the low voltage logic; andwriting to the fusible ROM using the second supply voltage generated by the high voltage supply. - View Dependent Claims (10, 11, 12)
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13. A machine-accessible medium having contained thereon a description of an integrated circuit, the integrated circuit comprising:
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a voltage detector circuit coupled to determine when a voltage supply is above a threshold logic level voltage; and a high voltage tolerant transistor (“
HVTT”
) having a gate coupled to receive a logic level voltage and a source and a drain coupled between a power rail and the voltage detector circuit, the HVTT to shelter the voltage detector circuit from voltages on the power rail above the logic level voltage, wherein the voltage detector includes;a first current path including a first resistive element and a first transistor coupled in series; a second current path including a second transistor and a second resistive element coupled in series, the first current path and the second current path coupled in parallel between the HVTT and a ground path; and a voltage comparator having first and second inputs, the first input coupled to a first node between the first transistor and the first resistive element and the second input coupled to a second node between the second transistor and the second resistive element, the comparator to compare a first voltage of the first node against a second voltage of the second node. - View Dependent Claims (14, 15)
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16. An integrated circuit, comprising:
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low voltage logic coupled to a first power rail and operable above a threshold logic level voltage, the first power rail to couple to a logic voltage supply to receive a logic level voltage; high voltage circuitry coupled to a second power rail and operable at a high level voltage, the second power rail to couple to a high voltage supply to receive the high level voltage, wherein the second power rail comprises a dual voltage power rail to switchably couple to both the high voltage supply and the logic voltage supply, the high level voltage above the logic level voltage and detrimental to the low voltage logic; and a high voltage tolerant (“
HVT”
) power up detector coupled to the first power rail and to the second power rail, the HVT power up detector to enable the low voltage logic when the first power rail is above a threshold logic level voltage, HVT power up detector to receive the high level voltage without detriment. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification