Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks
First Claim
1. A multi-functional device comprising:
- a plurality of analog blocks coupled in a single integrated circuit, said analog blocks organized into a plurality of segments, said plurality of analog blocks comprising first analog blocks in a first segment that are selectively and electrically coupled to and decoupled from second analog blocks in a second segment to implement a function, wherein different analog functions are implemented by selectively and electrically coupling different combinations of said plurality of analog blocks; and
a circuit coupled to said plurality of analog blocks, said circuit comprising a plurality of segment clock generators, said circuit operable to supply a synchronized clock signal from said plurality of segment clock generators to a combination of analog blocks comprising an analog block of said first segment and an analog block of said second segment, wherein all analog blocks in said combination of analog blocks are supplied with said synchronized clock signal.
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Accused Products
Abstract
A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.
81 Citations
13 Claims
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1. A multi-functional device comprising:
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a plurality of analog blocks coupled in a single integrated circuit, said analog blocks organized into a plurality of segments, said plurality of analog blocks comprising first analog blocks in a first segment that are selectively and electrically coupled to and decoupled from second analog blocks in a second segment to implement a function, wherein different analog functions are implemented by selectively and electrically coupling different combinations of said plurality of analog blocks; and a circuit coupled to said plurality of analog blocks, said circuit comprising a plurality of segment clock generators, said circuit operable to supply a synchronized clock signal from said plurality of segment clock generators to a combination of analog blocks comprising an analog block of said first segment and an analog block of said second segment, wherein all analog blocks in said combination of analog blocks are supplied with said synchronized clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification