Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks

• US 7,023,257 B1
• Filed: 10/01/2001
• Issued: 04/04/2006
• Est. Priority Date: 10/26/2000
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullam, Bert
• Primary Examiner(s): NGUYEN, MINH T
• Application Number:
  US09/969,313
• Time in Patent Office: 1,646 Days
• Field of Search: 327/291, 327/293, 327295-298, 327/144, 713/400, 713500-503
• US Class Current: 327/293
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.

Claims

1. A multi-functional device comprising:

a plurality of analog blocks coupled in a single integrated circuit, said analog blocks organized into a plurality of segments, said plurality of analog blocks comprising first analog blocks in a first segment that are selectively and electrically coupled to and decoupled from second analog blocks in a second segment to implement a function, wherein different analog functions are implemented by selectively and electrically coupling different combinations of said plurality of analog blocks; and

a circuit coupled to said plurality of analog blocks, said circuit comprising a plurality of segment clock generators, said circuit operable to supply a synchronized clock signal from said plurality of segment clock generators to a combination of analog blocks comprising an analog block of said first segment and an analog block of said second segment, wherein all analog blocks in said combination of analog blocks are supplied with said synchronized clock signal.

2. The multi-functional device of claim 1 wherein said plurality of analog blocks comprises switched capacitor blocks.

3. The multi-functional device of claim 1 comprising a domain clock generator coupled to said plurality of segment clock generators, wherein said domain clock generator supplies a plurality of clock signals at different frequencies to said segment clock generators.

4. The multi-functional device of claim 3 wherein said segment clock generators are operable to select one of said clock signals supplied by said domain clock generator.

5. The multi-functional device of claim 4 wherein a multiplexer is used by said segment clock generator to select one of said clock signals supplied by said domain clock generator.

6. The multi-functional device of claim 4 comprising a memory register coupled to said segment clock generators, wherein said one of said clock signals is selected according to information in said memory register.

7. The multi-functional device of claim 4 wherein said segment clock generators are operable to generate a two-phase non-overlapping clock signal from said one of said clock signals.

8. The multi-functional device of claim 7 wherein said segment clock generators are operable to change from said one of said clock signals to another clock signal and to establish phase alignment with said clock signals supplied by said domain clock generator.

9. The multi-functional device of claim 1 wherein each of said segment clock generators selects a clock signal from a plurality of clock signals.

10. The multi-functional device of claim 9 wherein said clock signals comprise clock signals at different frequencies.

11. The multi-functional device of claim 9 wherein each segment clock generator coupled to said combination of analog blocks selects a same clock signal.

12. The multi-functional device of claim 1 further comprising:

a bus coupled to said plurality of analog blocks;

a random access memory (RAM) coupled to said bus; and

a central processing unit (CPU) coupled to said bus, wherein said bus, RAM, CPU and plurality of analog blocks reside on a single chip.

13. The multi-functional device of claim 1 wherein said synchronized clock signal comprises a two-phase non-overlapping clock signal generated by said segment clock generators.