Coarse tuning for fractional-N synthesizers having reduced period comparison error

• US 7,023,282 B1
• Filed: 07/29/2004
• Issued: 04/04/2006
• Est. Priority Date: 05/11/2004
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Bunch, Ryan, Humpreys, Scott
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US10/901,546
• Time in Patent Office: 614 Days
• Field of Search: 331/1.A, 331/10, 331/11, 331/14, 331 16- 18, 331/25, 331/36.C, 331/177.R, 331/177.V, 331/179, 327156-159, 332/127, 360/51, 375/376, 455/260
• US Class Current: 331/1.00A
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer. During coarse tuning, a reference signal used to control an output frequency of the PLL is provided to the coarse tuning circuitry and is divided by a factor M to provide a divided reference signal. A controllable oscillator (CO) output signal from a CO in the PLL is divided by an N divider in the PLL to provide a divided CO signal. The periods or, equivalently, frequencies of the divided CO signal and the divided reference signal are compared, and the result is used to select an appropriate tuning curve for the CO. In order to reduce a period comparison error, synchronization circuitry operates to synchronize the N divider of the PLL and an M divider of the coarse tuning circuit.

Claims

1. A fractional-N frequency synthesizer comprising:

a) a phase lock loop (PLL) adapted to provide a CO output signal having a frequency determined by a reference signal and a divide value, the PLL comprising;

i) a controlled oscillator (CO) adapted to provide the CO output signal; and

ii) a first divider adapted to divide the CO output signal by the divide value to provide a divided CO signal;

b) coarse tuning circuitry comprising a second divider adapted to divide the reference signal by a factor M to provide a divided reference signal; and

c) synchronization circuitry adapted to synchronize the first and second dividers based on a clock signal derived from the CO output signal.

2. The fractional-N frequency synthesizer of claim 1 wherein the coarse tuning logic further comprises tuning logic adapted to compare a frequency of the divided reference signal and a frequency of the divided CO signal and effectuate coarse tuning of the CO based on the comparison.

3. The frequency synthesizer of claim 2 wherein the tuning logic is adapted to compare the frequency of the divided reference signal and the frequency of the divided CO signal by comparing the period of the divided reference frequency with the period of the divided CO frequency.

4. The fractional-N frequency synthesizer of claim 2 wherein the tuning logic provides a reset signal to the second divider and the synchronization circuitry provides a synchronized version of the reset signal to the first divider, thereby beginning the comparison of the frequency of the divided reference signal and the frequency of the divided CO signal.

5. The fractional-N frequency synthesizer of claim 4 wherein the first divider comprises:

a) prescaling circuitry adapted to receive the CO output signal and divide the CO output signal based on a modulus control signal to provide the clock signal; and

b) circuitry adapted to provide the divided CO signal and the modulus control signal based on the divide value, the clock signal, and the synchronized version of the reset signal.

6. The fractional-N frequency synthesizer of claim 4 wherein the first divider comprises:

a) prescaling circuitry adapted to receive the CO output signal and divide the CO output signal to provide the clock signal; and

b) circuitry adapted to provide the divided CO signal based on the divide value, the clock signal, and the synchronized version of the reset signal.

7. The fractional-N frequency synthesizer of claim 4 wherein the clock signal is the CO output signal and the first divider comprises:

a) prescaling circuitry adapted to receive the CO output signal and divide the CO output signal based on a modulus control signal to provide a scaled CO signal; and

b) circuitry adapted to provide the divided CO signal and the modulus control signal based on the divide value, the scaled CO signal, and the synchronized version of the reset signal.

8. The fractional-N frequency synthesizer of claim 1 wherein the clock signal has a frequency greater than the frequency of the reference signal.

9. The fractional-N frequency synthesizer of claim 1 wherein the clock signal is the CO output signal.

10. The fractional-N frequency synthesizer of claim 2 wherein the coarse tuning circuitry further comprises divide value generation circuitry adapted to:

a) provide an integer divide value to the first divider when operating in the integer division mode during coarse tuning; and

b) provide a fractional sequence of divide values to the first divider when operating in the fractional-N division mode during normal operation.

11. The fractional-N frequency synthesizer of claim 10 wherein the integer divide value is an integer component of a product of the multiplication of a desired divide value of the fractional-N synthesizer and the factor M.

12. The fractional-N frequency synthesizer of claim 10 wherein the tuning logic is further adapted to provide a tuning curve control signal to select a tuning curve for the CO of the PLL based on the comparison of the frequency of the divided reference signal and a frequency of the divided CO signal to effect coarse tuning of the CO.

13. The fractional-N frequency synthesizer of claim 12 wherein the tuning logic is further adapted to provide a control signal to the divide value generation circuitry, thereby controlling the mode of operation of the divide value generation circuitry.

14. The fractional-N frequency synthesizer of claim 12 wherein the CO comprises a circuit having a selectable capacitance with a plurality of settings corresponding to a plurality of tuning curves and the tuning logic is further adapted to provide the tuning curve control signal to sequentially select the plurality of tuning curves until the frequency of the divided CO signal is within a desired proximity of the frequency of the divided reference signal.

15. The fractional-N frequency synthesizer of claim 14 wherein the coarse tuning circuitry further comprises a coarse tune counter adapted to receive the tuning curve control signal and generate a select signal to provide to the circuit of the CO to control the selectable capacitance.

16. The frequency synthesizer of claim 12 wherein the coarse tuning circuitry further comprises a switch for coupling an initialization signal to a fine tuning signal for the CO to override feedback from a phase detector of the PLL during coarse tuning and bias the CO to operate at a predefined control setting.

17. The frequency synthesizer of claim 16 wherein the tuning logic is further adapted to control the switch.

18. A method for improving coarse tuning of a fractional-N frequency synthesizer comprising:

a) generating a controlled oscillator (CO) output signal based on a reference signal and a divide value;

b) dividing the CO output signal by the divide value to provide a divided CO signal;

c) dividing the reference signal by a factor M to provide a divided reference signal;

d) synchronizing dividing steps (b) and (c) based on a clock signal derived from the CO output signal; and

e) providing coarse tuning of a CO providing the CO output signal based on a comparison of the divided reference signal and the divided CO signal.

19. The method of claim 18 wherein the clock signal has a frequency greater than the frequency of the reference signal.

20. The method of claim 18 wherein the clock signal is the CO output signal.

21. The method of claim 18 wherein the dividing the reference signal step is controlled by a reset signal and the synchronizing step synchronizes the dividing steps (b) and (c) based on providing a synchronized version of the reset signal for controlling the dividing the CO signal step.

22. The method of claim 18 wherein the clock signal is a scaled version of the CO output signal.

23. The method of claim 18 further wherein the divide value is an integer divide value when operating in an integer division mode during coarse tuning, and the divide value is a fractional sequence of divide values when operating in a fractional-N division mode during normal operation.

24. The method of claim 23 wherein the integer divide value is an integer component of a product of the multiplication of a desired divide value of the fractional-N synthesizer and the factor M.

25. The method of claim 18 wherein the providing coarse tuning step comprises sequentially selecting a plurality of tuning curves of a CO providing the CO output signal until the frequency of the divided CO signal is within a desired proximity of the frequency of the divided reference signal.

26. The method of claim 18 wherein the providing coarse tuning step comprises comparing the frequency of the divided reference signal and the frequency of the divided CO signal by comparing the period of the divided reference frequency with the period of the divided CO frequency.