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Coarse tuning for fractional-N synthesizers having reduced period comparison error

  • US 7,023,282 B1
  • Filed: 07/29/2004
  • Issued: 04/04/2006
  • Est. Priority Date: 05/11/2004
  • Status: Active Grant
First Claim
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1. A fractional-N frequency synthesizer comprising:

  • a) a phase lock loop (PLL) adapted to provide a CO output signal having a frequency determined by a reference signal and a divide value, the PLL comprising;

    i) a controlled oscillator (CO) adapted to provide the CO output signal; and

    ii) a first divider adapted to divide the CO output signal by the divide value to provide a divided CO signal;

    b) coarse tuning circuitry comprising a second divider adapted to divide the reference signal by a factor M to provide a divided reference signal; and

    c) synchronization circuitry adapted to synchronize the first and second dividers based on a clock signal derived from the CO output signal.

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