Dual loop phase locked loop

• US 7,023,284 B2
• Filed: 04/17/2003
• Issued: 04/04/2006
• Est. Priority Date: 04/19/2002
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Suzuki, Ryoichi, Sogawa, Kazuaki
• Primary Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/485,861
• Publication Number:
  US 20040196107A1
• Time in Patent Office: 1,083 Days
• Field of Search: 331/10, 331/11, 331/14, 331/17, 331/18, 331/25, 327/141, 327/156, 327/162, 375/375, 375/376, 375/373
• US Class Current: 331/10
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

Claims

1. A dual loop PLL comprising:

a frequency comparison loop which includes a frequency comparator and a phase comparison loop which includes a phase comparator,

wherein in the frequency comparison loop, a frequency comparison between a reference frequency and an output frequency is performed based on a dichotomizing search method, and

wherein the frequency comparison loop includes;

the frequency comparator,

an up/down counter for incrementing or decrementing a count value according to a comparison result from the frequency comparator, and

a voltage controlled oscillator for changing the output frequency according to the count value of the up/down counter; and

the up/down counter includes;

a register for storing the count value,

an input control circuit for outputting a positive or negative value of a ½

of a previous addition/subtraction result value according to the comparison result from the frequency comparator, and

an adder for adding the count value of the register to the output of the input control circuit.

2. A dual loop PLL according to claim 1, wherein the frequency comparator includes an accuracy varying circuit for varying a frequency comparison accuracy for respective steps of the frequency comparison along with the progress of the dichotomizing search.

3. A dual loop PLL according to claim 1, wherein:

the frequency comparator is structured such that;

if the output frequency is equal to or lower than the reference frequency, the frequency comparator outputs an UP signal, and

if the output frequency is equal to or higher than the reference frequency, the frequency comparator outputs an DOWN signal; and

the up/down counter includes an error count prevention circuit for prohibiting an increment or decrement of the count value when the UP signal and DOWN signal are simultaneously received from the frequency comparator.

4. A dual loop PLL according to claim 1, wherein the frequency comparator avoids comparing a transient frequency, which occurs during the period when the voltage controlled oscillator controls a variation in the output frequency, with the reference frequency.

6. A dual loop PLL according to claim 1, wherein:

when the frequency comparison loop is formed, the voltage controlled oscillator receives a reference voltage having a predetermined value; and

the up/down counter includes a priority switch circuit which receives a comparison result from the frequency comparator and, if the reference frequency and the output frequency are equal to each other, priorly increments or decrements a count value according to a variation of the reference voltage from the predetermined value.

5. A dual loop PLL comprising:

a frequency comparison loop which includes a frequency comparator and a phase comparison loop which includes a phase comparator,

wherein in the frequency comparison loop, a frequency comparison between a reference frequency and an output frequency is performed based on a dichotomizing search method, and

wherein the phase comparison loop includes;

a voltage controlled oscillator, and

a loop filter placed at a stage previous to the voltage controlled oscillator; and

when the frequency comparison loop is formed,

the loop filter is disconnected from the voltage controlled oscillator, and

a reference voltage having a predetermined value is supplied to the loop filter and the voltage controlled oscillator.

7. A dual loop PLL comprising:

a frequency comparison loop which includes a frequency comparator and a phase comparison loop which includes a phase comparator,

a charge pump placed at a stage subsequent to the phase comparator;

a loop filter which is charged and discharged by the charge pump; and

a voltage controlled oscillator to which an input voltage is supplied from the loop filter,

wherein in the frequency comparison loop, a frequency comparison between a reference frequency and an output frequency is performed based on a dichotomizing search method, and

wherein in the frequency comparison mode, the charge pump supplies a reference voltage having a predetermined value to the loop filter, and in the phase comparison mode, the charge pump charges or discharges the loop filter according to an output of the phase comparator.

8. A dual loop PLL comprising:

a frequency comparison loop which includes a frequency comparator and a phase comparison loop which includes a phase comparator,

wherein in the frequency comparison loop, a frequency comparison between a reference frequency and an output frequency is performed based on a dichotomizing search method, and

wherein the phase comparison loop includes;

a charge pump placed at a stage subsequent to the phase comparator,

a loop filter placed at a stage subsequent to the charge pump; and

the loop filter includes;

a resistor having an end connected to the output side of the charge pump, and

a N-type transistor and a P-type transistor whose gate terminals are connected to the other end of the resistor,

wherein the N-type transistor has a source terminal, a drain terminal and a bulk terminal which are connected to ground, and the P-type transistor has a source terminal, a drain terminal and a bulk terminal which are connected to a power supply.

9. A dual loop PLL, comprising:

a frequency comparison loop which includes a frequency comparator and a phase comparison loop which includes a phase comparator,

wherein in the frequency comparison loop, a frequency comparison between a reference frequency and an output frequency is performed based on a dichotomizing search method, and

the frequency comparator in the frequency comparison loop includes an accuracy varying circuit for varying a frequency comparison accuracy for respective steps of the frequency comparison along with the progress of the dichotomizing search.