Array substrate for IPS mode liquid crystal display device and method for fabricating the same

• US 7,023,515 B2
• Filed: 01/23/2004
• Issued: 04/04/2006
• Est. Priority Date: 12/24/2001
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Ik-Soo, Chae, Gee-Sung
• Primary Examiner(s): NGO, HUYEN LE
• Application Number:
  US10/762,327
• Publication Number:
  US 20040150779A1
• Time in Patent Office: 802 Days
• Field of Search: 349/38, 349/39, 349/43, 349/139, 349/141
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

An array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device includes a pixel electrode having an extension portion, a vertical portion and a horizontal portion, the extension portion being extended from the drain electrode to the pixel region, the vertical portion being vertically extended from the extension portion and the horizontal portion being over the common line and being connected to the vertical portion. The device includes a common electrode having a plurality of vertical portions and a horizontal portion, the plurality of the vertical portions being vertically extended from the common line and arranged in an alternating pattern with the vertical portion of the pixel electrode, the horizontal portion connecting the plurality of the vertical portions into one. An auxiliary line is over the horizontal portion of the pixel electrode and being overlapped with the common line.

Claims

1. An array substrate for in-plane switching mode liquid crystal display device, comprising:

a substrate having a plurality of pixel regions;

a gate line, a gate electrode, a common line and a common electrode on the substrate;

a first insulating layer over the substrate;

a semiconductor layer on the first insulating layer;

a data line, source and drain electrodes and a pixel electrode on the substrate including the semiconductor layer, the pixel electrode and the common electrode in each pixel region, the common line and the pixel electrode forming a first storage capacitor;

a second insulating layer over the substrate;

an auxiliary line on the second insulating layer and overlapping the common line, the pixel electrode and the auxiliary line forming a second storage capacitor; and

a dummy line in a non-display area of the substrate,

wherein the dummy line is connected to the auxiliary line.

2. The array substrate according to claim 1, wherein the dummy line includes one of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), molybdenum (Mo), copper (Cu) and chromium (Cr).

3. The array substrate according to claim 1, wherein the auxiliary line includes one of Indium-Tin-Oxide (ITO) and Indium Zinc Oxide (IZO).

4. The array substrate according to claim 1, wherein the gate line, the common line and the common electrode are formed using the same material on a same layer.

5. The array substrate according to claim 1, wherein the gate line, the common line and the common electrode include one of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), molybdenum (Mo), copper (Cu) and chromium (Cr).

6. The array substrate according to claim 1, wherein the first an insulating layer is between the common line and the pixel electrode to form the first auxiliary storage capacitor.

7. The array substrate according to claim 6, wherein the first insulating layer includes one of silicon nitride (SiNx) and silicon oxide (SiO₂).

8. The array substrate according to claim 1, wherein the second insulating layer is between the pixel electrode and the auxiliary line to form the second storage capacitor.

9. The array substrate according to claim 8, wherein the second insulating layer includes one of silicon nitride (SiNx) and silicon oxide (SiO₂).

10. The array substrate according to claim 1, wherein a thin film transistor includes the gate electrode, the semiconductor layer, the source electrode and the drain electrode.