Methods of increasing the reliability of a flash memory

• US 7,023,735 B2
• Filed: 06/16/2004
• Issued: 04/04/2006
• Est. Priority Date: 06/17/2003
• Status: Active Grant

• Current Assignee: Ramot at Tel Aviv University Limited (Tel Aviv University)
• Original Assignee: Ramot at Tel Aviv University Limited (Tel Aviv University)
• Inventors: Alrod, Idan, Litsyn, Simon, Ban, Amir
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/867,646
• Publication Number:
  US 20050013171A1
• Time in Patent Office: 657 Days
• Field of Search: 365/185.2
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

A multi-level flash memory cell is read by comparing the cell'"'"'s threshold voltage to a plurality of integral reference voltages and to a fractional reference voltage. Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell'"'"'s threshold voltages to fractional reference voltages.

Claims

1. A method of operating a flash memory cell, comprising the steps of:

(a) programming the cell to store data; and

(b) subsequent to said programming, reading the cell by steps including;

(i) comparing a threshold voltage of the cell to at least one integral reference voltage; and

(ii) comparing said threshold voltage of the cell to at least one fractional reference voltage.

2. The method of claim 1, further comprising the step of:

(c) providing a plurality of said integral reference voltages; and

wherein said comparing of said threshold voltage of the cell to said at least one fractional reference voltage is effected only if said comparing of said threshold voltage of the cell to said at least one integral reference voltage indicates that said threshold voltage of the cell is higher than a lowest of said integral reference voltages and lower than a highest of said integral reference voltages.

3. The method of claim 1, further comprising the step of:

(c) providing a plurality of said integral reference voltages; and

wherein, if said comparing of said threshold voltage of the cell to said plurality of integral reference voltages indicates that said threshold voltage of the cell is between two consecutive said integral reference voltages, then said at least one fractional reference voltage also is between said two consecutive integral reference voltages.

4. A flash memory device, comprising:

(a) at least one flash memory cell; and

(b) a controller operative to operate each said flash memory cell by steps including;

(i) programming the cell to store data, and

(ii) subsequent to said programming, reading the cell by steps including;

(A) comparing a threshold voltage of said each flash memory cell to at least one integral reference voltage, and

(B) comparing said threshold voltage of said each flash memory cell to at least one fractional reference voltage.

5. A method of storing data, comprising the steps of:

(a) providing n cells, of a multi-level flash memory, that are operative to store at least m>

1 bits each; and

(b) for each integer p from 0 through m−

1;

(i) programming a number k(p)≦

n of said cells to store k(p) bits of the data as bits of significance level p, and

(ii) if k(p)<

n, programming a remaining n−

k(p) of said cells to store n−

k(p) corresponding redundancy bits as bits of significance level p;

wherein said number k(p), for at least one value of said integer p, has a value different from that of said number k(p) for at least one other value of said integer p.

6. A flash memory device, comprising:

(a) n flash memory cells operative to store at least m>

1 bits each; and

(b) a controller operative to store data in said cells by, for each integer p from 0 through m−

1;

(i) programming a number k(p)≦

n of said cells to store k(p) bits of the data as bits of significance level p, and

(ii) if k(p)<

n, programming a remaining n−

k(p) of said cells to store n−

k(p) corresponding redundancy bits as bits of significance level p;

with said number k(p), for at least one value of said integer p, having a value different from that of said number k(p) for at least one other value of said integer p.

7. A method of storing and retrieving data, comprising the steps of:

(a) providing n cells, of a multi-level flash memory, that are operative to store at least m>

1 bits each;

(b) for each integer p from 0 through m−

1;

(i) programming a number k(p)≦

n of said cells to store k(p) bits of the data as bits of significance level p, and

(ii) if k(p)<

n, programming a remaining n−

k(p) of said cells to store n−

k(p) corresponding redundancy bits as bits of significance level p;

(c) reading said n cells to determine provisional retrieved values of said stored bits; and

(d) for each integer p from 0 through m−

1;

if k(p)<

n;

(i) correcting said provisional retrieved values of said bits of significance level p according to said provisional retrieved values of said redundancy bits of significance level p, thereby providing final retrieved values of said bits of significance level p, and

(ii) if p is less than m−

1, adjusting said provisional retrieved values of said bits of significance levels p+1 through m−

1 contingent on said final retrieved values of said bits of significance level p.

8. The method of claim 7, wherein k(p) is a nondecreasing function of p.

9. The method of claim 7, wherein, for each of said n cells, said reading of said each cell is effected by steps including comparing a threshold voltage of said each cell to a plurality of integral reference voltages.

10. The method of claim 9, wherein, subsequent to said correcting of said provisional retrieved values of said bits of significance level 0, for each of said n cells, said adjusting of said provisional retrieved values of said bits of significance levels 1 through m−

1 is effected in accordance with a comparison of said threshold value of said each cell to a fractional reference voltage.

11. The method of claim 9, wherein, for each of said n cells, said comparing of said threshold voltage of said each cell to said plurality of integral reference voltages assigns said threshold voltage of said each cell to a voltage band of said each cell, and wherein, subsequent to said correcting of said provisional retrieved values of said bits of significance level 0<

p<

m−

1, for each of said n cells, said adjusting of said provisional retrieved values of said bits of significance levels p+1 through m−

1 is effected by a minimal reassignment of said voltage band to which said threshold voltage of said each cell is assigned.

12. The method of claim 11, wherein, if two said reassignments are minimal reassignments, said adjusting of said provisional retrieved values of said bits of significance levels p+1 through m−

1 is effected by said reassignment that sets said provisional retrieved value of said bit of significance level p+1 equal to said provisional retrieved value of said bit of significance level p−

1.

13. The method of claim 11, wherein, if two said reassignments are minimal reassignments, said adjusting of said provisional retrieved values of said bits of significance levels p+1 through m−

1 is effected by said reassignment that sets said provisional retrieved value of said bit of significance level p+1 equal to said final retrieved value of said bit of significance level p−

1.

14. A flash memory device, comprising:

(a) n flash memory cells operative to store at least m>

1 bits each; and

(b) a controller operative to store and retrieve data from said cells by;

(i) for each integer p from 0 through m−

1;

(A) programming a number k(p)≦

n of said cells to store k(p) bits of the data as bits of significance level p, and

(B) if k(p)<

n, programming a remaining n−

k(p) of said cells to store n−

k(p) corresponding redundancy bits as bits of significance level p,

(ii) reading said n cells to determine provisional retrieved values of said stored bits, and

(iii) for each integer p from 0 through m−

1;

if k(p)<

n;

(A) correcting said provisional retrieved values of said bits of significance level p according to said provisional retrieved values of said redundancy bits of significance level p, thereby providing final retrieved values of said bits of significance level p, and

(B) if p is less than m−

1, adjusting said provisional retrieved values of said bits of significance levels p+1 through m−

1 contingent on said final retrieved values of said bits of significance level p.

15. A method of storing data, comprising the steps of:

(a) providing n cells, of a multi-level flash memory, that are operative to store at least two significance groups of bits, each said significance group including bits of a respective number q≧

1 of consecutive significance levels; and

(b) for each said significance group;

(i) programming said cells to store a respective number k≦

nq bits of the data as bits having significance levels within said each significance group, and

(ii) if k is less than nq, programming said cells to store nq−

k corresponding redundancy bits as bits having significance levels within said each significance group;

wherein said number k, for at least one said significance group, has a value different from that of said number k for at least one other said significance group.

16. A flash memory device, comprising:

(a) n flash memory cells operative to store at least two significance groups of bits, each said significance group including bits of a respective number q≧

1 of consecutive significance levels; and

(b) a controller operative to store and retrieve data from said cells by, for each said significance group;

(i) programming said cells to store a respective number k≦

nq bits of said data as bits having significance levels within said each significance group, and

(ii) if k is less than nq, programming said cells to store nq−

k corresponding redundancy bits as bits having significance levels within said each significance group;

with said number k, for at least one said significance group, having a value different from that of said number k for at least one other said significance group.

17. A method of storing and retrieving data, comprising the steps of:

(a) providing n cells, of a multi-level flash memory, that are operative to store at least two significance groups of bits, each said significance group including bits of a respective number q≧

1 of consecutive significance levels;

(b) for each said significance group;

(i) programming said cells to store a respective number k≦

nq bits of the data as bits having significance levels within said each significance group, and

(ii) if k is less than nq, programming said cells to store nq−

k corresponding redundancy bits as bits having significance levels within said each significance group;

(c) reading said n cells to determine provisional retrieved values of said stored bits; and

(d) for each said significance group;

if said respective number k is less than nq;

(i) correcting said provisional retrieved values of said bits that have significance levels within said each significance group according to said provisional retrieved values of said redundancy bits that have significance levels within said each significance group, thereby providing final retrieved values of said bits that have significance levels within said each significance group, and

(ii) for each said significance group other than a most significant said significance group, adjusting said provisional retrieved values of said bits of significance groups more significant than said each significance group contingent on said final retrieved values of said bits that have significance levels within said each significance group.

18. A flash memory device, comprising:

(a) n flash memory cells operative to store at least two significance groups of bits, each said significance group including bits of a respective number q≧

1 of consecutive significance levels; and

(b) a controller operative to store and retrieve data from said cells by;

(i) for each said significance group;

(A) programming said cells to store a respective number k≦

nq bits of said data as bits having significance levels within said each significance group, and

(B) if k is less than nq, programming said cells to store nq−

k corresponding redundancy bits as bits having significance levels within said each significance group,

(ii) reading said n cells to determine provisional retrieved values of said stored bits, and

(iii) for each said significance group;

if said respective number k is less than nq;

(A) correcting said provisional retrieved values of said bits that have significance levels within said each significance group according to said provisional retrieved values of said redundancy bits that have significance levels within said each significance group, thereby providing final retrieved values of said bits that have significance levels within said each significance group, and

(B) for each said significance group other than a most significant said significance group, adjusting said provisional retrieved values of said bits of significance groups more significant than said each significance group contingent on said final retrieved values of said bits that have significance levels within said each significance group.

19. A method for storing and retrieving a binary number, comprising the steps of:

(a) providing a memory including a number n, greater than 1, of cells, each said cell having a respective adjustable threshold voltage;

(b) setting said threshold voltages to collectively represent the number;

(c) estimating said threshold voltages by steps including comparing said threshold voltages to at least one fractional reference voltage; and

(d) decoding said estimated threshold voltages collectively to recover the number.

20. A storage device for storing a binary number of b bits, comprising:

(a) a memory having a plurality n of m-bits-per-cell cells, n being smaller than b/m;

(b) a plurality of adjustable threshold voltages used to represent the bits;

(c) a storing mechanism to collectively set said adjustable threshold voltages to store the number in said memory; and

(d) a retrieving mechanism to collectively estimate said threshold voltages by steps including comparing said threshold voltages to at least one fractional reference voltage in order to retrieve the number from said memory.