NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same

• US 7,023,739 B2
• Filed: 12/05/2003
• Issued: 04/04/2006
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G., Nallamothu, Sucheta, Walker, Andrew J., Chen, En-Hsing, Ilkbahar, Alper
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/729,844
• Publication Number:
  US 20050122780A1
• Time in Patent Office: 851 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.17, 365/185.19, 365/185.28
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Claims

1. A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said modifiable conductance switch devices comprising thin film transistor (TFT) devices, said method comprising pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block.

2. The method of claim 1 further comprising performing a read operation only after at least two programming pulses.

3. The method of claim 1 further comprising maintaining an inhibit voltage on associated array lines between programming pulses.

4. The method of claim 1 wherein the leakage current effects include changes in a voltage bias at one or more locations within a NAND string that otherwise may occur during a long programming pulse.

5. The method of claim 4 further comprising re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.

12. The method of claim 1 further comprising:

coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell; and

de-coupling the selected NAND string from other associated array lines.

13. The method of claim 12 wherein the de-coupling the selected NAND string step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.

14. The method of claim 13 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

15. The method of claim 13 wherein the turning off step comprises driving to different levels respective select signals corresponding to at least two respective ones of the plurality of series select devices at the end of the selected NAND string.

16. The method of claim 15 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.

20. The method of claim 1 wherein the memory array comprises a three-dimensional memory array having at least two planes of memory cells formed above a substrate.

21. The method of claim 20 further comprising performing a read operation only after at least two programming pulses.

22. The method of claim 20 further comprising maintaining an inhibit voltage on associated array lines between programming pulses.

23. The method of claim 20 further comprising re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.

24. The method of claim 20 further comprising:

coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and

de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.

25. The method of claim 24 further comprising maintaining the inhibit voltage on the associated array lines between programming pulses.

26. The method of claim 24 further comprising:

driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage;

then

decoupling the unselected NAND strings from the associated array lines conveying the inhibit voltage; and

pulsing the selected word line to the programming voltage.

27. The method of claim 26 wherein:

the selected word line is brought to ground before decoupling unselected NAND strings from the associated array lines conveying the inhibit voltage, and then driven to the programming voltage.

28. The method of claim 24 wherein the de-coupling unselected NAND strings step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.

29. The method of claim 28 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

30. The method of claim 20 further comprising:

coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell; and

de-coupling the selected NAND string from other associated array lines.

31. The method of claim 30 wherein the de-coupling the selected NAND string step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.

32. The method of claim 31 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

33. The method of claim 31 wherein the turning off step comprises driving to different levels respective select signals corresponding to at least two respective ones of the plurality of series select devices at the end of the selected NAND string.

34. The method of claim 33 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.

35. The method of claim 20 wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.

36. The method of claim 20 wherein the programming voltage is within the range from 10 to 16 volts.

37. The method of claim 20 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.

38. The method of claim 37 wherein NAND strings of a given memory plane include selection devices formed above the substrate.

39. The method of claim 1 wherein the modifiable conductance switch devices comprise transistors having a depletion mode threshold voltage at least some of the time.

40. The method of claim 1 wherein the modifiable conductance switch devices comprise devices chosen from the group consisting of:

a device including a floating gate electrode;

a device including silicon nanoparticles;

a device including a polarizable material; and

a device including a ferroelectric material.

42. The method of claim 1 wherein the modifiable conductance switch devices have more than two nominal values of conductance, for storing more than one bit of data per memory cell.

6. A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising:

pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block;

coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and

de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.

7. The method of claim 6 further comprising maintaining the inhibit voltage on the associated array lines between programming pulses.

8. The method of claim 6 further comprising:

driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage;

then

decoupling the unselected NAND strings from the associated array lines conveying the inhibit voltage; and

pulsing the selected word line to the programming voltage.

9. The method of claim 8 wherein:

the selected word line is brought to ground before decoupling unselected NAND strings from the associated array lines conveying the inhibit voltage, and then driven to the programming voltage.

10. The method of claim 6 wherein the de-coupling unselected NAND strings step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.

11. The method of claim 10 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

19. The method of claim 6 wherein the memory array comprises a two-dimensional memory array having one plane of memory cells formed in a substrate.

41. The method of claim 6 wherein the modifiable conductance switch devices comprise thin film transistor (TFT) devices.

17. A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising:

pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block;

wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.

18. A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising:

pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block;

wherein the programming voltage is within the range from 10 to 16 volts.

43. A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising:

pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block;

wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

44. The method of claim 43 wherein the charge storage dielectric comprises an oxide-nitride-oxide (ONO) stack.

45. The method of claim 43 wherein the transistors have a depletion mode threshold voltage for at least one of two data states.

46. An integrated circuit comprising:

a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said modifiable conductance switch devices comprising thin film transistor (TFT) devices;

array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block.

47. The integrated circuit of claim 46 wherein the array support circuitry is further configured for performing a read operation only after at least two programming pulses.

48. The integrated circuit of claim 46 wherein the array support circuitry is further configured for maintaining an inhibit voltage on associated array lines between programming pulses.

49. The integrated circuit of claim 46 wherein the leakage current effects include changes in a voltage bias at one or more locations within a NAND string that otherwise may occur during a long programming pulse.

50. The integrated circuit of claim 49 wherein the array support circuitry is further configured for re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.

57. The integrated circuit of claim 46 further comprising means for coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell.

58. The integrated circuit of claim 57 further comprising means for turning off at least one of a plurality of series select devices at an end of the selected NAND strings.

59. The integrated circuit of claim 58 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

60. The integrated circuit of claim 58 wherein the respective select signals corresponding to at least two respective ones of the plurality of series select devices at the end of the selected NAND string are driven to different levels.

61. The integrated circuit of claim 60 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.

65. The integrated circuit of claim 46 wherein the memory array comprises a three-dimensional memory array having at least two planes of memory cells formed above a substrate.

66. The integrated circuit of claim 65 further comprising:

means for performing a read operation only after at least two programming pulses; and

means for maintaining an inhibit voltage on associated array lines between programming pulses.

67. The integrated circuit of claim 65 further comprising means for re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.

68. The integrated circuit of claim 65 further comprising:

means for coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and

means for de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.

69. The integrated circuit of claim 68 further comprising means for maintaining the inhibit voltage on the associated array lines between programming pulses.

70. The integrated circuit of claim 68 further comprising:

means for driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage;

means for then decoupling, before the selected word line programming pulse, the unselected NAND) strings from the associated array lines conveying the inhibit voltage.

71. The integrated circuit of claim 68 comprising a plurality of series select devices at an end of each NAND string.

72. The integrated circuit of claim 71 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

73. The integrated circuit of claim 65 further comprising:

means for coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell.

74. The integrated circuit of claim 65 further comprising means for driving to different levels respective select signals corresponding to at least two respective ones of a plurality of series select devices at the end of the selected NAND string.

75. The integrated circuit of claim 74 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.

76. The integrated circuit of claim 65 wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.

77. The integrated circuit of claim 65 wherein the programming voltage is within the range from 10 to 16 volts.

78. The integrated circuit of claim 65 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.

79. The integrated circuit of claim 78 wherein NAND strings of a given memory plane include selection devices formed above the substrate.

80. The integrated circuit of claim 65 wherein the substrate comprises a polycrystalline substrate.

81. The integrated circuit of claim 65 wherein the substrate comprises an insulating substrate.

82. The integrated circuit of claim 46 wherein the modifiable conductance switch devices comprise transistors having a depletion mode threshold voltage at least some of the time.

83. The integrated circuit of claim 46 including modifiable conductance switch devices chosen from the group consisting of:

a device including a floating gate electrode;

a device including silicon nanoparticles;

a device including a polarizable material; and

a device including a ferroelectric material.

85. The integrated circuit of claim 46 wherein the modifiable conductance switch devices have more than two nominal values of conductance, for storing more than one bit of data per memory cell.

51. An integrated circuit comprising:

a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices;

array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; and

means for coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage to establish a bias condition within such unselected NAND strings.

52. The integrated circuit of claim 51 wherein the array support circuitry is further configured for maintaining the inhibit voltage on the associated array lines between programming pulses.

53. The integrated circuit of claim 51 further comprising:

means for driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage;

means for then decoupling, before the selected word line programming pulse, the unselected NAND strings from the associated array lines conveying the inhibit voltage.

54. The integrated circuit of claim 51 comprising a respective plurality of series select devices at an end of each NAND string.

55. The integrated circuit of claim 51 further comprising means for turning off at least one of a plurality of series select devices at an end of the selected NAND strings.

56. The integrated circuit of claim 54 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.

64. The integrated circuit of claim 51 wherein the memory array comprises a two-dimensional memory array having one plane of memory cells formed in a substrate.

84. The integrated circuit of claim 51 wherein the modifiable conductance switch devices comprise thin film transistor (TFT) devices.

62. An integrated circuit comprising:

a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices;

array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block, wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.

63. An integrated circuit comprising:

a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices;

array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block, wherein the programming voltage is within the range from 10 to 16 volts.

86. An integrated circuit comprising:

a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; and

array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block;

wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.

87. The integrated circuit of claim 86 wherein the charge storage dielectric comprises an oxide-nitride-oxide (ONO) stack.

88. The integrated circuit of claim 86 wherein the transistors have a depletion mode threshold voltage for at least one of two data states.