Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage

• US 7,023,751 B2
• Filed: 01/19/2005
• Issued: 04/04/2006
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Kirsch, Howard C.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US11/040,959
• Publication Number:
  US 20050141309A1
• Time in Patent Office: 440 Days
• Field of Search: 365/205, 365/189.09, 365/177
• US Class Current: 365/205
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations

Abstract

The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.

Claims

1. A memory array, comprising:

a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;

a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective colunm of memory cells;

a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;

a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier being operable to couple a first voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a first logic level, and being operable to couple a second voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a second logic level, the first voltage being a positive supply voltage and the second voltage being a positive supply voltage having a magnitude that is significantly less than the magnitude of the first voltage; and

a voltage regulator coupled to the respective sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor and being operable to supply the first and second voltages to the sense amplifier, the second voltage being supplied using the at least one bipolar transistor.

2. The memory array of claim 1 wherein each of the sense amplifiers comprises:

a p-sense amplifier powered by the first voltage; and

an n-sense amplifier powered by the second voltage.

3. The memory array of claim 2 wherein a pair of complementary digit lines are provided for each column of memory cells, and wherein the p-sense amplifier and the n-sense amplifier for the respective column is coupled to both of the complementary digit lines.

4. The memory array of claim 1 wherein the first logic level comprises a logic “

1,” and

the second logic level comprises a logic “

0.”

5. The memory array of claim 1 wherein the second voltage is less than 1 volt.

6. The memory array of claim 5 wherein the second voltage is less than 0.3 volts.

7. The memory array of claim 1 wherein the digit lines comprise folded digit lines in which a pair of complimentary digit lines are provided for each column of memory cells in the memory array.

8. The memory array of claim 1 wherein the digit lines comprise open digit lines in which a single digit line is provided for each column of memory cells in the memory array.

9. A dynamic random access memory (“

DRAM”

), comprising;

a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;

an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals;

a memory array from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals, the memory array comprising;

a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;

a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective column of memory cells;

a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;

a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier being operable to couple a first voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a first logic level, and being operable to couple a second voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a second logic level, the first voltage being a positive supply voltage and the second voltage being a positive supply voltage having a magnitude that is significantly less than the magnitude of the first voltage; and

a voltage regulator coupled to the respective sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor and being operable to supply the first and second voltages to the sense amplifier, the second voltage being supplied using the at least one bipolar transistor; and

a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling data signals to and from the memory array.

10. The DRAM of claim 9 wherein each of the sense amplifiers comprises:

a p-sense amplifier powered by the first voltage; and

an n-sense amplifier powered by the second voltage.

11. The DRAM of claim 10 wherein a pair of complementary digit lines are provided for each column of memory cells, and wherein the p-sense amplifier and the n-sense amplifier for the respective column is coupled to both of the complementary digit lines.

12. The DRAM of claim 9 wherein the first logic level comprises a logic “

1,” and

the second logic level comprises a logic “

0.”

13. The DRAIVI of claim 9 wherein the second voltage is less than 1 volt.

14. The DRAM of claim 13 wherein the second voltage is less than 0.3 volts.

15. The DRAM of claim 9 wherein the digit lines comprise folded digit lines in which a pair of complimentary digit lines are provided for each column of memory cells in the memory array.

16. The DRAM of claim 9 wherein the digit lines comprise open digit lines in which a single digit line is provided for each column of memory cells in the memory array.

17. A processor-based system, comprising:

an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a dynamic random access memory coupled to a processor bus, the dynamic random access memory comprising;

a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;

an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; and

a memory array from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals, the memory array comprising;

a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;

a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective column of memory cells;

a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;

a sense amplifier for each colunm of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier being operable to couple a first voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a first logic level, and being operable to couple a second voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a second logic level, the first voltage being a positive supply voltage and the second voltage being a positive supply voltage having a magnitude that is significantly less than the magnitude of the first voltage; and

a voltage regulator coupled to the respective sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor and being operable to supply the first and second voltages to the sense amplifier, the second voltage being supplied using the at least one bipolar transistor; and

a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling data signals to and from the memory array.

18. The processor-based system of claim 17 wherein each of the sense amplifiers comprises:

a p-sense amplifier powered by the first voltage; and

an n-sense amplifier powered by the second voltage.

19. The processor-based system of claim 18 wherein a pair of complementary digit lines are provided for each column of memory cells, and wherein the p-sense amplifier and the n-sense amplifier for the respective column is coupled to both of the complementary digit lines.

20. The processor-based system of claim 17 wherein the first logic level comprises a logic “

1,” and

the second logic level comprises a logic “

0.”

21. The processor-based system of claim 17 wherein the second voltage is less than 1 volt.

22. The processor-based system of claim 21 wherein the second voltage is less than 0.3 volts.

23. The processor-based system of claim 17 wherein the digit lines comprise folded digit lines in which a pair of complimentary digit lines are provided for each column of memory cells in the memory array.

24. The processor-based system of claim 17 wherein the digit lines comprise open digit lines in which a single digit line is provided for each column of memory cells in the memory array.

25. A method of reducing the sub threshold leakage of access transistors in a dynamic random access memory (“

DRAM”

) array fabricated in a semiconductor substrate and having at least one digit line for each column, the access transistors for each column being coupled to the respective at least one digit line for the column, the method comprising;

fabricating at least one bipolar transistor in the semiconductor substrate in a manner that isolates the bipolar transistor from a portion of the semiconductor substrate in which the access transistors are fabricated, the at least one bipolar transistor being part of a voltage regulator circuit that generates a regulated output voltage; and

selectively coupling the regulated output voltage to the at least one digit line for each column.

26. The method of claim 25 wherein the DRAM array further comprises a respective sense amplifier for each column coupled to the at least one digit line for the respective column, and wherein the act of selectively coupling the regulated output voltage to the at least one digit line for each column comprises coupling the regulated output voltage to the at least one digit line by using the regulated output voltage to power the sense amplifiers.

27. The method of claim 26 wherein the at least one bipolar transistor includes a collector, and wherein the act of selectively coupling the regulated output voltage to the at least one digit line for each column comprises coupling the collector to respective power inputs for the sense amplifiers.

28. The method of claim 26 wherein the respective sense amplifiers for each column comprise n-sense amplifiers, and wherein the regulated output voltage comprises a positive voltage.

29. The method of claim 28 wherein the regulated output voltage comprises a positive voltage having a magnitude that is substantially less than the magnitude of a positive supply voltage applied to the DRAM array.

30. The method of claim 25 wherein the act of fabricating at least one bipolar transistor in the semiconductor substrate in a manner that isolates the bipolar transistor from a portion of the semiconductor substrate in which the access transistors are fabricated comprises fabricating the at least one bipolar transistor in a well that is fabricated in the semiconductor substrate.

31. The method of claim 25 wherein the act of selectively coupling the regulated output voltage to the at least one digit line for each column comprises coupling the regulated output voltage to the at least one digit line for each column when an access transistor coupled to the respective digit line is non-conductive.

32. The method of claim 25 wherein the act of fabricating at least one bipolar transistor in the semiconductor substrate comprises fabricating two bipolar transistors in the semiconductor substrate and coupling the bipolar transistors to each other as a Darlington pair.

33. A method of supplying power to a plurality of sense amplifiers fabricated in a semiconductor substrate, each of the sense amplifiers being provided for a respective column of an array of dynamic random access memory cells, the sense method comprising:

fabricating at least one bipolar transistor in the semiconductor substrate in a manner that isolates the bipolar transistor from a portion of the semiconductor substrate in which the sense amplifiers are fabricated, the at least one bipolar transistor being part of a voltage regulator circuit that generates a regulated output voltage; and

coupling the regulated output voltage to the sense amplifiers.

34. The method of claim 33 wherein the at least one bipolar transistor includes a collector, and wherein the act of coupling the regulated output voltage to the sense amplifiers comprises coupling the collector to respective power inputs for the sense amplifiers.

35. The method of claim 33 wherein the respective sense amplifiers for each column comprise n-sense amplifiers, and wherein the regulated output voltage comprises a positive voltage.

36. The method of claim 33 wherein the regulated output voltage comprises a positive voltage having a magnitude that is substantially less than the magnitude of a positive supply voltage applied to the DRAM array.

37. The method of claim 33 wherein the act of fabricating at least one bipolar transistor in the semiconductor substrate in a manner that isolates the bipolar transistor from a portion of the semiconductor substrate in which the sense amplifiers are fabricated comprises fabricating the at least one bipolar transistor in a well that is fabricated in the semiconductor substrate.

38. The method of claim 33 wherein the act of fabricating at least one bipolar transistor in the semiconductor substrate comprises fabricating two bipolar transistors in the semiconductor substrate and coupling the bipolar transistors to each other as a Darlington pair.

39. In a dynamic random access memory (“

DRAM”

) fabricated in a semiconductor substrate, the DRAM memory having an array of memory cells arranged in rows and columns, the DRAM memory further having at least one digit line for each column of the array, a respective access transistor coupling each of the memory cells to the at least one digit line for the respective column, a respective p-sense amplifier coupled to the at least one digit line for each column of the array, and a respective n-sense amplifier coupled to the at least one digit line for each column of the array, a method of supplying power to the p-sense amplifiers and the n-sense amplifiers so that a sub threshold leakage the access transistors is reduced, the method comprising;

fabricating a well in the semiconductor substrate in a manner that electrically isolates the well from the substrate;

fabricating at least one bipolar transistor in the well, the at least one bipolar transistor being part of a voltage regulator circuit that generates a regulated output voltage;

coupling the regulated output voltage to respective power inputs of the n-sense amplifiers; and

coupling a positive voltage having a first magnitude to respective power inputs of the p-sense amplifiers.

40. The method of claim 39 wherein the at least one bipolar transistor includes a collector, and wherein the act of coupling the regulated output voltage to respective power inputs of the n-sense amplifiers comprises coupling the collector to respective power inputs of the n-sense amplifiers.

41. The method of claim 39 wherein the regulated output voltage comprises a positive voltage.

42. The method of claim 41 wherein the regulated output voltage comprises a positive voltage having a magnitude that is substantially less than the first magnitude of the positive voltage that is coupled to the power inputs of the p-sense amplifiers.

43. The method of claim 39 wherein the act of fabricating at least one bipolar transistor in the well comprises fabricating two bipolar transistors in the well and coupling the bipolar transistors to each other as a Darlington pair.