Voice gateway with downstream voice synchronization
First Claim
1. A method of synchronizing data sampled by a first clock to a second clock, comprising:
- periodically generating a data received flag as a function of said first clock and a data complete flag as a function of said second clock;
generating a clock error signal as a function of said data received and data complete flags; and
fractionally resampling the data as a function of the clock error signal, wherein the clock error signal generation comprises counting at least a portion of a period between data receive flags and counting at least a portion of a period between data complete flags, the fractional resampling being a function of ratio of counts.
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Accused Products
Abstract
A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC, and a USB controller to provide high performance and robust operation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
113 Citations
26 Claims
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1. A method of synchronizing data sampled by a first clock to a second clock, comprising:
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periodically generating a data received flag as a function of said first clock and a data complete flag as a function of said second clock; generating a clock error signal as a function of said data received and data complete flags; and fractionally resampling the data as a function of the clock error signal, wherein the clock error signal generation comprises counting at least a portion of a period between data receive flags and counting at least a portion of a period between data complete flags, the fractional resampling being a function of ratio of counts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A synchronization circuit, comprising:
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an error generation unit that generates a clock error signal as a; and a sample tracker adapted to receive sampled data packets, wherein the sample tracker fractionally resamples the sampled data as a function of the clock error signal, wherein said error generation unit comprises one or more counters incremented by a local reference clock, a first latch adapted to store count of at least a portion of a cycle between packet arrivals, a second latch adapted to store at least a portion of a cycle between packet completions, wherein said clock error signal is a function of ratio of packet arrival count and packet completion count. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A network gateway adapted to exchange voice signals between a network line at a first clock frequency and a packet based network at a second clock frequency, comprising:
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a network port to interface with the packet based network; a telephony port to interface with a telephony device; a processor coupled to each of the ports; and a voice synchronizer coupled between said network and telephony ports and comprising an error generation unit for generating a clock error signal in accordance with ratio of said first and second clocks and a sample tracker, and adapted to receive data packets, wherein the sample tracker fractionally resamples the received data as a function of the clock error signal. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification