Notch filter for DC offset reduction in radio-frequency apparatus and associated methods

• US 7,024,221 B2
• Filed: 02/12/2002
• Issued: 04/04/2006
• Est. Priority Date: 01/12/2001
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Tuttle, G. Tyson, Behrens, Richard T., Vishakhadatta, G. Diwakar, Kerth, Donald A., Srinivasan, Vishnu S., Spurbeck, Mark S., Paulus, Tod
• Primary Examiner(s): Gesesse, Tilahun
• Assistant Examiner(s): Lee, John J.
• Application Number:
  US10/075,099
• Publication Number:
  US 20020168951A1
• Time in Patent Office: 1,512 Days
• Field of Search: 455/74, 455/553.1, 455/73, 455/75, 455/86, 455/131, 455/88, 455/550.1, 455/139, 455/157.1, 455/158.2, 455/164.1, 455/232.1, 455/241.1, 455/243.1, 375/216, 375/319, 375/324, 375/348, 375/259
• US Class Current: 455/553.1
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry coupled together. The receiver analog circuitry receives an RF signal. The receiver analog circuitry processes the received RF signal and generates a digital signal that it provides to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal. The digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry.

Claims

1. A receiver digital circuitry, comprising:

digital down-converter circuitry configured to mix a digital input signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal; and

digital filter circuitry configured to filter the digital down-converted signal to generate a filtered digital signal,

wherein the digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry, and

wherein the digital filter circuitry provides the notch by using a notch filter circuitry that has one or more poles the locations of which are adjustable over an adjustment cycle of the notch filter circuitry, and wherein the locations of the one or more poles of the notch filter circuitry are adjusted in an initial part of the adjustment cycle of the notch filter circuitry so that the notch filter circuitry tends to settle quickly.

2. The receiver digital circuitry of claim 1, wherein the locations of the one or more poles of the notch filter circuitry are further adjusted in a latter part of the adjustment cycle of the notch filter circuitry so that the notch filter circuitry tends to produce a narrow notch.

3. The receiver digital circuitry of claim 2, wherein the locations of the one or more poles of the notch filter circuitry are adjusted by modifying at least one filter coefficient of the notch filter circuitry.

4. The receiver digital circuitry of claim 3, wherein the locations of the one or more poles of the notch filter circuitry are adjusted before a reception of a burst of data by the receiver digital circuitry begins.

5. The receiver digital circuitry of claim 4, wherein the intermediate frequency local oscillator signal comprises a digital signal.

6. The receiver digital circuitry of claim 5, wherein the digital filter circuitry further comprises:

a cascade integrator/comb filter circuitry configured to receive and filter the digital down-converted signal, the cascade integrator/comb filter circuitry further configured to provide a cascade integrator/comb filter circuitry output signal; and

a secondary filter circuitry configured to receive and filter the cascade integrator/comb filter circuitry output signal, the secondary filter circuitry further configured to provide the filtered digital signal.

7. The receiver digital circuitry of claim 6, wherein the secondary filter circuitry further comprises the notch filter circuitry and at least one biquad filter circuitry configured to receive and filter an output signal of the notch filter circuitry.

8. The receiver digital circuitry of claim 7 used in a radio-frequency transceiver circuitry.

9. A radio-frequency (RF) receiver circuitry, comprising:

receiver analog circuitry included within a first integrated circuit, the receiver analog circuitry configured to receive and process a radio-frequency input signal to generate a processed radio-frequency signal, the receiver analog circuitry further configured to use an analog-to-digital converter circuitry to convert the processed radio-frequency signal into a digital output signal; and

receiver digital circuitry, included within a second integrated circuit and coupled to the receiver analog circuitry within the first integrated circuit, the receiver digital circuitry configured to receive and process the digital output signal to generate a processed digital signal, the receiver digital circuitry further configured to provide a notch in a frequency spectrum of the processed digital signal,

wherein the receiver digital circuitry provides the notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry by using a notch filter circuitry configured to provide the notch, and wherein the notch filter circuitry provides the notch at minus a frequency of an intermediate frequency local oscillator signal.

10. The radio-frequency receiver circuitry of claim 9, wherein the notch filter circuitry has one or more poles the locations of which are adjustable so as to modify the settling time and notch width of the notch filter circuitry.

11. The radio-frequency receiver circuitry of claim 10, wherein the locations of the one or more poles of the notch filter circuitry are adjusted at an initial point in time so that the notch filter circuitry tends to settle quickly.

12. The radio-frequency receiver circuitry of claim 11, wherein the locations of the one or more poles of the notch filter circuitry are adjusted at least once more after the initial point in time so that the notch filter circuitry tends to produce a progressively narrow notch.

13. The radio-frequency receiver circuitry of claim 12, wherein the locations of the one or more poles of the notch filter circuitry are adjustable by modifying at least one filter coefficient of the notch filter circuitry.

14. The radio-frequency receiver circuitry of claim 13, wherein adjustment of the locations of the one or more poles of the notch filter circuitry completes before a reception of a burst of data by the receiver digital circuitry begins.

15. The radio-frequency receiver circuitry of claim 14, wherein the intermediate frequency local oscillator signal comprises a digital signal.

16. The radio-frequency receiver circuitry of claim 15, used within a radio-frequency transceiver circuitry.

17. The radio-frequency receiver circuitry of claim 15, further comprising digital programmable gain amplifier circuitry configured to apply a programmable gain to the processed digital signal to produce a scaled digital signal.

18. The radio-frequency receiver circuitry of claim 17, further comprising a baseband processor circuitry coupled to the receiver digital circuitry, the baseband processor circuitry configured to receive the scaled digital signal.

19. The radio-frequency receiver circuitry of claim 18, used within a radio-frequency transceiver circuitry.

20. The radio-frequency receiver circuitry of claim 17, further comprising digital-to-analog converter circuitry configured to convert the scaled digital signal to an analog signal.

21. The radio-frequency receiver circuitry of claim 20, further comprising a baseband processor circuitry coupled to the receiver digital circuitry, the baseband processor circuitry configured to receive the analog signal.

22. The radio-frequency receiver circuitry of claim 21, used within a radio-frequency transceiver circuitry.

23. A method of receiving a radio-frequency (RF) signal, comprising:

receiving and processing the radio-frequency signal to generate an analog processed radio-frequency signal;

converting the analog processed radio-frequency signal to a digital signal; and

processing the digital signal by providing a notch at a frequency that corresponds to a residual DC offset in the analog processed radio-signal by using a notch filter circuitry that has one or more poles the locations of which are adjustable so as to modify the settling time and notch width of the notch filter circuitry, and wherein the notch filter circuitry has one or more poles the locations of which are adjustable so as to modify the settling time and notch width of the notch filter circuitry.

24. The method of claim 23, wherein providing the notch further includes adjusting the locations of the one or more poles of the notch filter circuitry at an initial point in time so that the notch filter circuitry tends to settle quickly.

25. The method of claim 24, wherein providing the notch further comprises adjusting the locations of the one or more poles of the notch filter circuitry at least once more after the initial point in time so that the notch filter circuitry tends to produce a progressively narrow notch.

26. The method of claim 25, wherein providing the notch further comprises adjusting the locations of the one or more poles of the notch filter circuitry by modifying at least one filter coefficient of the notch filter circuitry.

27. The method of claim 26, wherein providing the notch further comprises completing the adjustment of the locations of the one or more poles of the notch filter circuitry before a reception of a burst of data by the receiver digital circuitry begins.

28. The method of claim 27, further comprising applying a programmable gain to the processed signal to produce an scaled digital signal.

29. The method of claim 28, further comprising providing the scaled digital signal to a baseband processor circuitry.

30. The method of claim 28, further comprising converting the scaled digital signal to an analog signal.

31. The method of claim 30, further comprising providing the analog signal to a baseband processor circuitry.