Chip management system

• US 7,024,636 B2
• Filed: 11/20/2002
• Issued: 04/04/2006
• Est. Priority Date: 11/20/2002
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Weed, Dan
• Primary Examiner(s): Garbowski, Leigh M.
• Application Number:
  US10/301,182
• Publication Number:
  US 20040098689A1
• Time in Patent Office: 1,231 Days
• Field of Search: 716 1- 2, 716 4- 5, 716/11, 716/18, 706919-921, 706/45, 706/47, 706/60, 700/119, 700/121, 700 95-107
• US Class Current: 716/102
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/31 Design entry, e.g. editors specifically adapted for circuit design
• CPC Class Codes: Y10S 706/921 Layout, e.g. circuit, construction

Abstract

A method and system for automatically guiding a user through a design flow for an integrated circuit are disclosed. The method and system include displaying a design flow user interface on a user'"'"'s computer, where the user interface includes symbols corresponding to design flow process steps. The design flow process steps are defined with a set of rules, and user input for each step is analyzed for compliance with the rules. The user is allowed to proceed to a next step in the flow once it is determined that the previous steps have been completed successfully.

Claims

1. A web-based expert system for automatically guiding a user through a design flow for a chip, the method comprising:

(a) displaying a design flow user interface on a user'"'"'s computer, where the user interface includes symbols for user selection corresponding to a sequence of design flow process steps, the steps including any combination of “

Initial Analysis and Fit to Slice,”

“

Import Cores and IP”

“

RapidWorks Tools,”

“

Simulation and Timing Models,”

“

Chip Place and Route,” and

“

Data Check and Preparation for Manufacturing”

, wherein once selected at least a portion of the design flow process steps require the user to enter input;

(b) defining the design flow process steps with a set of rules, and analyzing whether the user input for each step requiring user input complies with the rules; and

(c) allowing the user to proceed to a next step in the sequence of design flow process steps if it is determined that previous steps have been completed successfully.

2. The method of claim 1 wherein step (a) further includes the step of:

providing each process block with nested levels of process screens.

3. The method of claim 2 wherein step (a) further includes the step of:

displaying on the user interface a navigational tree showing the thumbnail images of upper-level process blocks to provide the user a quick reference as to which step is being displayed in relation to the overall flow.

4. The method of claim 3 wherein step (a) further includes the step of:

displaying color-coded thumbnails to indicate completed process blocks.

5. A computer-readable medium containing programming instructions for a web-based expert system that automatically guides a user through a design flow for a chip, the program instructions for:

(a) displaying a design flow user interface on a user'"'"'s computer, where the user interface includes symbols for user selection corresponding to a sequence of design flow process steps, the steps including any combination of “

Initial Analysis and Fit to Slice,”

“

Import Cores and IP,”

“

RapidWorks Tools,”

“

Simulation and Timing Models,”

“

Chip Place and Route,” and

“

Data Check and Preparation for Manufacturing”

, wherein once selected at least a portion of the design flow process steps require the user to enter input;

(b) defining the design flow process steps with a set of rules, and analyzing whether the user input for each step requiring user input complies with the rules; and

(c) allowing the user to proceed to a next step in the sequence of design flow process steps if it is determined that previous steps have been completed successfully.

6. The computer-readable medium of claim 5 further including the instruction of guiding the user through a design flow for an ASIC, wherein the design flow process instructions include “

Entry of the Design,”

“

Logic synthesis,”

“

System Partitioning,”

Prelayout simulation,”

“

Floor Planning,”

“

Placement,”

“

Routing,”

“

Circuit Extraction,” and

“

Post Layout Simulation”

.

7. The computer-readable medium of claim 5 further including the instruction of defining the design flow process instructions to include design, business systems including inventory status updates, and release to manufacturing instructions, such that the expert system manages both the design and manufacturing of the integrated circuit.

8. The computer-readable medium of claim 7 wherein the symbols are displayed as process blocks, instruction (a) further including the instruction of:

displaying a status indicator in each process block indicating completions status of that block to the user.

9. The computer-readable medium of claim 8 wherein instruction (a) further includes the instruction of:

providing each process block with nested levels of process screens.

10. The computer-readable medium of claim 9 wherein instruction (a) further includes the instruction of:

displaying on the user interface a navigational tree showing the thumbnail images of upper-level process blocks to provide the user a quick reference as to which instruction is being displayed in relation to the overall flow.

11. The computer-readable medium of claim 10 wherein instruction (a) further includes the instruction of:

displaying color-coded thumbnails to indicate completed process blocks.