Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)

• US 7,024,653 B1
• Filed: 10/30/2000
• Issued: 04/04/2006
• Est. Priority Date: 10/30/2000
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moore, Michael T., Lie, James
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/703,181
• Time in Patent Office: 1,982 Days
• Field of Search: 716 1- 21, 326/41, 326/47, 326/101, 710/10, 713/1, 713/100, 370/366, 709/221
• US Class Current: 716/121
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

According to one embodiment, an integrated circuit (100) includes a programmable portion (102) and a communication portion (104). A programmable portion (102) may include logic circuits that are configurable by a user. A communication portion (104) may include one or more circuit blocks designed to perform predetermined serial data communication functions. According to one embodiment, a communication portion (104) may include a block converter (218) that can encode/decode input data words into output data words, and a scrambler circuit (220) for scrambling/de-scrambling data according to a predetermined scrambling polynomial value. Different scrambling polynomial values may be selected from an operation control store (206) to provide a variety of different scrambling/de-scrambling functions. The inclusion of a communication portion (104) may reduce the size and/or increase the speed of an integrated circuit over conventional approaches that may synthesize serial data communication functions from programmable logic circuits.

Claims

1. An integrated circuit device, comprising:

a programmable portion comprising a plurality of circuits configurable by a user of the integrated circuit device; and

at least one communication portion comprising;

a plurality of data operation circuits, each of which performs a different function on received input data, including at least one circuit block manufactured to perform a predetermined data communication function including converting received first data values into second data values, the at least one circuit including a block converter circuit that converts an input data word into an output data word having different bit values than the input data word in response to a user selectable operational value, and

an operation control store that provides the user selectable operational value from a plurality of operational values to the at least one circuit to control the type of operation performed on the received data; and

a memory circuit for storing configuration information for configuring circuits of the programmable portion.

2. The integrated circuit device of claim 1, wherein:

the programmable portion comprises a programmable interconnect portion and a logic gate portion.

3. The integrated circuit device of claim 1, further including:

a timing circuit that receives a clock signal and generates an internal clock signal that is phase shifted with respect to the clock signal.

4. The integrated circuit device of claim 1, further including:

a plurality of input/outputs commonly connected to the programmable portion and the communication portion.

5. The integrated circuit device of claim 1, wherein:

the data operation circuits include a scrambler circuit that performs a scramble operation on the received data represented by a scrambling polynomial.

6. The integrated circuit device of claim 1, wherein:

the data operation circuits include a scrambler circuit that performs a scramble operation on the received data; and

the operation control store provides operational values that represent at least one scrambling polynomial.

7. The integrated circuit device of claim 1, wherein:

the operational control store includes circuits that provides at least one user operational value configured by a user and preset operational values that are established by at least one integrated circuit manufacturing step.

8. The integrated circuit device of claim 1, wherein:

the communication portion includes a data (MUX) multiplexer that enables a data path between one of a plurality of inputs and a data MUX output, and each data operation circuit is coupled to an input of the data MUX.

9. The integrated circuit device of claim 1, wherein:

the communication portion includes a physical layer circuit that provides a data output stream compatible with a particular data transmission media.

10. The integrated circuit device of claim 1, wherein:

the at least one communication portion includes a plurality of communication portions.

11. A semiconductor device, comprising:

a programmable logic device having a communication portion embedded therein, the communication portion including non-programmable circuits designed to provide a selectable data communication function,

the non-programmable circuits comprising a block converter circuit that encodes input data words into output data words and a scrambler circuit that scrambles data values according to a user selectable scrambling polynomial, and

an operational control store that provides the user selectable scrambling polynomial value to the scrambler circuit from a plurality of user selectable scrambling polynomial values.

12. The semiconductor device of claim 11, wherein:

the communication portion includes a plurality of circuit blocks that each provides a different data communication function.

13. The semiconductor device of claim 12, wherein:

the communication portion includes a selectable data path between each circuit block and a data output.

14. The semiconductor device of claim 11, wherein:

the communication portion includes a block converter circuit that decodes input data words into output data words and a de-scrambler circuit that de-scrambles data values according to an operational control value provided by the operational control store.

15. A method, comprising the steps of:

performing predetermined logic functions on a programmable logic portion of an integrated circuit; and

performing serial data communication functions on a communication portion of the integrated circuit that includes circuit blocks that are not synthesized with programmable logic device configuration data, the serial data communication functions being user selectable between

(i) selectin a polynomial value from a number of user selectable polynomial values, and

scrambling serial data according to the selected polynomial value, or

(ii) encoding serial data having words of a first bit length into serial data having words of a second bit length that is different than the first bit length.