Method for reducing wafer arcing

• US 7,026,174 B2
• Filed: 09/30/2002
• Issued: 04/11/2006
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Fischer, Andreas
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): UMEZ ERONINI, LYNETTE T
• Application Number:
  US10/261,403
• Publication Number:
  US 20040063316A1
• Time in Patent Office: 1,289 Days
• Field of Search: 438/14, 438/706, 438/707, 438/710, 438/712, 361/234
• US Class Current: 438/14
• CPC Class Codes: H01J 2237/0206 Extinguishing, preventing or controlling unwanted discharges
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/6831 using electrostatic chucks

Abstract

A method for reducing wafer damage during an etching process is provided. In one of the many embodiments, the method includes assigning a bias voltage to each of at least one etching process, and generating the assigned bias voltage before initiation of one of the at least one etching process. The method further includes applying the assigned bias voltage to an electrostatic chuck before initiation of one of the at least one etching processes. The assigned bias voltage level reduces wafer arcing.

Claims

1. A method for reducing wafer damage during an etching process, comprising:

assigning a first bias voltage from a plurality of bias voltages, wherein each one of the plurality of bias voltages correspond to at least one of a plurality of etching processes;

generating the assigned bias voltage before initiation of a selected one of the plurality of etching processes;

applying the assigned bias voltage to an electrostatic chuck before initiation of the selected one of the plurality of etching processes; and

performing the selected one of the plurality of etching processes;

wherein the assigned bias voltage generates a voltage differential between adjacent metal structures within a dielectric of the wafer, wherein the voltage differential is less than an electrical breakdown strength of the dielectric layer when the selected one of the plurality of etching processes is being performed.

2. A method for reducing wafer damage during an etching process as recited in claim 1, wherein the etching process includes etching a low-k dielectric.

3. A method for reducing wafer damage during an etching process as recited in claim 1, wherein the assigning includes determining the bias voltage that reduced wafer arcing for the selected at least one etching process.

4. A method for reducing wafer damage during an etching process as recited in claim 1, wherein generating the assigned bias voltage includes:

determining the selected etching process to be utilized,

matching the the selected etching process to a corresponding assigned bias voltage;

generating a recipe setting signal including the assigned bias voltage.

5. A method for reducing wafer damage during an etching process as recited in claim 1, wherein applying the assigned bias voltage includes applying the assigned bias voltage to electrodes in the electrostatic chuck.

6. A method for reducing wafer damage during an etching process as recited in claim 1, wherein the bias voltage reduces a voltage potential between a wafer surface and a wafer substrate.

7. A method for reducing wafer damage during an etching process as recited in claim 1, wherein the bias voltage assigned to the selected etching process is stored in a recipe bias table.

8. A method for reducing wafer damage during an etching process, comprising:

generating a recipe bias table that includes associations between each one of a plurality of bias voltages and each one of a plurality of etching processes;

determining a first etching process from the plurality of etching processes to be conducted;

matching the first etching process to a corresponding first bias voltage by using the associations in a recipe table;

generating the first bias voltage;

applying the first bias voltage to an electrostatic chuck before initiation of the first etching process; and

performing the first etching process;

wherein the one of the first bias voltage generates a voltage differential between adjacent metal structures within a dielectric of the wafer, wherein the voltage differential is less than an electrical breakdown strength of the dielectric layer when the first etching processes is being performed.

9. A method for reducing wafer damage during an etching process as recited in claim 8, wherein the first etching process includes etching a low-k dielectric.

10. A method for reducing wafer damage during an etching process as recited in claim 8, wherein the recipe table is stored in software.

11. A method for reducing wafer damage during an etching process as recited in claim 8, wherein applying the assigned bias voltage includes applying the assigned bias voltage to electrodes in the electrostatic chuck.

12. A method for reducing wafer damage during an etching process as recited in claim 8, wherein the bias voltage reduces a voltage potential between a wafer surface and a wafer substrate.

13. A method for reducing wafer damage during an etching process as recited in claim 8, further comprising:

completing the first etching process;

ceasing applying the first bias voltage to the electrostatic chuck;

determining a second etching process from the plurality of etching processes to be conducted;

matching the second etching process to a corresponding second bias voltage by using the associations in a recipe table;

generating the second bias voltage;

applying the second bias voltage to the electrostatic chuck before initiation of the second etching process; and

performing the second etching process;

wherein the one of the second bias voltage generates a voltage differential between adjacent metal structures within a dielectric of the wafer, wherein the voltage differential is less than an electrical breakdown strength of the dielectric layer when the second etching processes is being performed.

14. A method for reducing wafer damage during an etching process as recited in claim 8, wherein the bias voltage is applied to the electrostatic chuck through electrodes disposed inside the electrostatic chuck.

15. A method for reducing wafer damage during an etching process as recited in claim 8, wherein electrostatic chuck contains a ceramic material.

16. A method for determining bias voltage for reducing wafer damage during an etching process, comprising:

determining a first etching process to be conducted; and

matching the first etching process to a corresponding first bias voltage by using associations in a recipe table which includes associations between each one of a plurality of bias voltages and a corresponding each one of a plurality of etching processes process, wherein the one of the first bias voltage generates a voltage differential between adjacent metal structures within a dielectric of the wafer, wherein the voltage differential is less than an electrical breakdown strength of the dielectric layer when the first etching processes is being performed.

17. A method for determining bias voltage for reducing wafer damage as recited in claim 16, wherein the first etching process includes etching a low-k dielectric.

18. A method for determining bias voltage for reducing wafer damage as recited in claim 16, wherein the recipe table is stored in software.

19. A method for determining bias voltage for reducing wafer damage as recited in claim 16, wherein the bias voltage reduces a voltage potential between a wafer surface and a wafer substrate.

20. A computer readable media having program instructions for determining bias voltage for reducing wafer damage where a bias voltage setting circuit determines the bias voltage that a voltage bias generator applies to an electrostatic chuck during etching to reduce wafer arcing, the computer readable media comprising:

program instructions for determining a first etching process to be conducted; and

program instructions for matching the first etching process to a corresponding first bias voltage by using associations in a recipe table which includes associations between each one of a plurality of bias voltages and a corresponding each one of a plurality of etching processes, wherein the one of the first bias voltage generates a voltage differential between adjacent metal structures within a dielectric of the wafer, wherein the voltage differential is less than an electrical breakdown strength of the dielectric layer when the first etching processes is being performed.

21. A computer readable media having program instructions as recited in claim 20, wherein the first etching process includes etching a low-k dielectric.

22. A computer readable media having program instructions as recited in claim 20, wherein the bias voltage reduces a voltage potential between a wafer surface and a wafer substrate.