Mold making method for wafer scale caps

• US 7,026,176 B2
• Filed: 12/08/2003
• Issued: 04/11/2006
• Est. Priority Date: 01/10/2001
• Status: Expired due to Term

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): MITCHELL, JAMES M
• Application Number:
  US10/728,923
• Publication Number:
  US 20040082115A1
• Time in Patent Office: 855 Days
• Field of Search: None
• US Class Current: 438/15
• CPC Class Codes: B29C 2035/0822 using IR radiation
• CPC Class Codes: B29C 2043/503 using ejector pins, rods
• CPC Class Codes: B29C 33/0022 Multi-cavity moulds B29C33/301 takes precedence
• CPC Class Codes: B29C 33/3842 Manufacturing moulds, e.g. shaping the mould surface by machining
• CPC Class Codes: B29C 43/36 Moulds for making articles of definite length, i.e. discrete articles
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0127 Using a carrier for applying a plurality of packaging lids to the system wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

Disclosed is a method for fabricating a mold. The mold is used for protective caps which will be applied to a wafer. The method comprises the steps of fabricating first and second cooperating mold halves from a semiconductor material using lithography. The first half and second half, when brought together define mold cavities for the wafer scale protective caps.

Claims

1. A method of fabricating a mold for protective caps which are to be attached to a wafer, the method comprising the steps of:

fabricating a first and a second cooperating mold halves from a semiconductor material using lithography, the first and second cooperating mold halves being fabricated from the same material as the wafer;

the first half and second halves, when brought together defining an array of mold cavities for an array of wafer scale protective caps, the array of mold cavities having a spacing which corresponds to a spacing provided on the wafer.

2. The method of claim 1, wherein:

at least one half includes ejection holes;

the method further comprising the provision of an eject wafer having pins; and

locating the ejection wafer behind the half so that the pins enter the holes.

3. The method of claim 1, wherein:

the material is silicon.

4. The method of claim 1, wherein:

the mold cavities are formed using cryogenic deep silicon etching techniques.

5. The method of claim 1, wherein:

the first half of the mold has a lower surface in which recesses are formed;

the second mold half having an upper surface in which grooves are formed;

the recesses and grooves defining the mold cavities.

6. The method of claim 1, wherein:

the first half has formed in it first eject holes;

there being provided a first half release wafer from which projects a number of pins;

locating the pins in registry with the first holes;

the first half having a thickness in the area of the first holes, the pins being longer than the thickness;

the first half release wafer having a first position in which the pins are flush with an interior end of the first holes; and

providing a gap between the first half and the first half release wafer when the first half release wafer is in the first position.

7. The method of claim 6, wherein:

the holes are formed by electron beam or X-ray lithography.

8. The method of claim 6, wherein:

the first and second halves and the first half release wafer are comprised of a semiconductor that is transparent to infrared light of a wavelength of about 1000–

5000 nm.

9. The method of claim 6, wherein:

the pins are formed by electron beam or X-ray lithography.

10. The method of claim 1, wherein:

the second half includes second eject holes formed through it;

there being provided a second half release wafer from which project pins;

locating the pins in registry with the second eject holes;

the second half having a thickness in the area of the second eject holes, the pins being longer than the thickness;

the second half release wafer having a first position in which the pins are flush with an interior end of the second eject holes;

there being a second gap between the second half and the second half release wafer when the second half release wafer is in the first position.

11. The method of claim 1, wherein:

the first and second halves are comprised of a semiconductor that is transparent to infrared light of a wavelength of about 1000–

5000 nm.

12. The method of claim 1, wherein the first half includes first holes formed through it, and further comprising the steps of:

providing a first half release wafer from which project pins;

locating the pins in alignment with the first holes;

the first half having a thickness in the area of the first holes, the pins being formed longer than the thickness;

the first half release wafer having a first position in which the pins are flush with an interior end of the first holes;

locating a gap between the first half and the first half release wafer when the first half release wafer is in the first position;

forming second holes through the second half;

providing a second half release wafer from which projects pins;

locating the pins in alignment with the second holes;

the second half having a thickness in the area of the second holes, the pins being formed longer than the thickness;

the second half release wafer having a first position in which the pins are flush with an interior end of the second holes;

locating a second gap between the second half and the second half release wafer when the second half release wafer is in the first position.

13. The method of claim 12, wherein:

the pins and holes are formed by electron beam or X-ray lithography.

14. The method of claim 12, wherein:

the first and second halves and the first and second half release wafers are comprised of a semiconductor that is transparent to infrared light of a wavelength of about 1000–

5000 nm.

15. The method of claim 1, wherein:

locating in the first half, portions which separate adjacent areas;

locating in the second half, cooperating portions which separate adjacent mold features;

the portions and cooperating portions coming together when the halves are brought together such that material is squeezed out from between the first and second portions, separating adjacent caps.

16. The method of claim 15, wherein:

the portions and cooperating portions are formed by electron beam or X-ray lithography.

17. The method of claim 15, wherein:

the portions and cooperating portions have un-etched top surfaces.

18. The method of claim 1, wherein:

locating in the first half, portions which separate adjacent areas;

locating in the second half cooperating portions which separate adjacent mold features;

the portions and cooperating portions coming together when the halves are brought together such that material is left as a thin layer between the first and second portions, the caps thus being intended, initially, as an array joined by the thin layer.