Transistor with reduced gate-to-source capacitance and method therefor

• US 7,026,204 B2
• Filed: 03/24/2004
• Issued: 04/11/2006
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Brech, Helmut
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/807,624
• Publication Number:
  US 20050212064A1
• Time in Patent Office: 748 Days
• Field of Search: 438/197, 438/268, 438/273, 257/341
• US Class Current: 438/197
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line at tabs adjacent to the finger gate over the active area, typically over the source, but the tabs add gate-to-source capacitance. This was previously quite small but as gate dielectrics have gotten thinner there is more capacitive coupling to the substrate by the tabs, and as gates have gotten thinner there is more resistance in the polysilicon finger gates. Both have the effect of increasing the RC time constant of the gate finger. This increase in RC time constant is alleviated by increasing the thickness of the dielectric separating the tabs from the substrate thereby reducing the capacitance caused by the tabs.

Claims

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate having an active area;

forming an insulating layer over the active area;

selectively removing portions of the insulating layer to leave a plurality of tab insulators in the active area;

forming a gate dielectric over the active area;

forming a first layer over the gate dielectric;

patterning the first layer to form a gate finger, a plurality of gate tabs adjacent to the gate finger, and a plurality of tab connections connecting the plurality of gate tabs to the gate finger; and

connecting the plurality of gate tabs together.

2. The method of claim 1, wherein the connecting is further characterized as forming a metal line that is connected to the plurality of gate tabs.

3. The method of claim 2, wherein the tab insulators have a thickness greater than that of the gate dielectric.

4. The method of claim 3, wherein the thickness of the tab insulators is at least about four times greater than the thickness of the gate dielectric.