Parasitic capacitance-preventing dummy solder bump structure and method of making the same

• US 7,026,234 B2
• Filed: 06/08/2004
• Issued: 04/11/2006
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Kuo-Ming, Liu, Hung-Min, Jao, Jui-Meng, Wang, Kun-Chih, Sheu, Shing-Ren
• Primary Examiner(s): Baumeister, B. William
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US10/709,940
• Publication Number:
  US 20040266160A1
• Time in Patent Office: 672 Days
• Field of Search: 438/613, 438/614, 438/622, 438/623, 438/624, 438/626, 438/612, 257/758, 257/707, 257/737, 257/738, 257/778, 257/780
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Claims

1. A parasitic capacitance-preventing dummy solder bump structure, the dummy solder bump structure being formed on a substrate, the dummy solder bump structure comprising:

at least one conductive layer formed on the substrate;

a dielectric layer formed on the substrate to cover the conductive layer;

a passivation layer formed on the dielectric layer to completely cover the dielectric layer;

an under bump metallurgy layer (UBM layer) directly formed on the surface of the passivation layer without a metal pad there in between; and

a solder bump formed on the UBM layer.

2. The dummy solder bump structure of claim 1 wherein the substrate is a semiconductor wafer with circuits formed inside the semiconductor wafer, and the passivation layer is formed by a chemical vapor deposition (CVD) process.

3. The dummy solder bump structure of claim 1 wherein the dielectric layer and the passivation layer comprise either silicon nitride or silicon oxide.

4. The dummy solder bump structure of claim 1 wherein the UBM layer is a metal layer formed by a sputtering process.

5. The dummy solder bump structure of claim 1 wherein a plurality of solder bump structures is formed on the passivation layer.

6. The dummy solder bump structure of claim 5 wherein each of the solder bump structures comprises:

a metal pad formed on the passivation layer;

an UBM layer formed on the metal pad; and

a solder bump formed on the UBM layer.

7. The dummy solder bump structure of claim 6 wherein each of the solder bump structures comprises at least one via plug for electrically connecting the solder bump structure with a corresponding portion of the conductive layer below the solder bump structure.

8. The dummy solder bump structure of claim 5 wherein the solder bump structure is positioned in a central area of a surface of the substrate, and the dummy solder bump structures are positioned in a border area of the surface of the substrate to surround at least one of the solder bump structures.

9. The dummy solder bump structure of claim 1 wherein the dummy solder bump structure is employed to improve the fluidity of an underfill liquid compound in subsequent packaging processes.

10. The dummy solder bump structure of claim 1 wherein the UBM layer dose not contact with the conductive layer.

11. A method of forming a solder bump on a substrate, the substrate comprising at least one conductive layer positioned on a surface of the substrate, the surface of the substrate comprising a first area and a second area, the method comprising:

performing a CVD process to form a dielectric layer on the substrate to cover the conductive layer;

forming a passivation layer on the surface of the dielectric layer to completely cover the dielectric layer;

forming at least one via plug only in portions of the dielectric layer and the passivation layer within the first area down to a surface of the conductive layer;

forming at least one metal pad only in portions of the passivation layer within the first area, the metal pad being electrically connected to the via plug;

performing an UBM process to form at least one UBM layer on the metal pad within the first area and at least one UBM layer directly on the surface of the passivation layer without a metal pad there in between within the second area; and

forming a solder bump on each of the UBM layers.

12. The method of claim 11 wherein the dielectric layer and the passivation layer comprise either silicon nitride or silicon oxide.

13. The method of claim 11 wherein the via plug comprises either one of titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), copper (Cu) or copper-aluminum alloy (Cu—

Al alloy).

14. The method of claim 11 wherein the UBM layer is formed by performing a sputtering process.

15. The method of claim 11 wherein the solder bump formed within the second area is employed as a dummy solder bump to improve the fluidity of an underfill liquid compound in subsequent packaging processes.

16. The method of claim 11 wherein the substrate is a semiconductor wafer with circuits formed inside the semiconductor wafer.

17. The method of claim 11 wherein the first area and the second area are respectively a central area and a border area of the surface of the substrate.