Semiconductor inspection system

• US 7,026,615 B2
• Filed: 02/13/2003
• Issued: 04/11/2006
• Est. Priority Date: 04/27/2001
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yoshida, Shoji, Yoda, Haruo, Ikeda, Mitsuji, Takane, Atsushi, Ozawa, Yasuhiko
• Primary Examiner(s): Lee, John R.
• Assistant Examiner(s): Johnston, Phillip A.
• Application Number:
  US10/365,383
• Publication Number:
  US 20030173516A1
• Time in Patent Office: 1,153 Days
• Field of Search: 250/310
• US Class Current: 250/310
• CPC Class Codes: H01J 37/28 with scanning beams H01J37/268, H01J37/292, H01J37/2955 take precedence

Abstract

An operator-free and fully automated semiconductor inspection system with high throughput is realized. All conditions required for capturing and inspection are generated from design information such as CAD data. In order to perform actual inspection under the conditions, a semiconductor inspection system is composed of a navigation system for generating all the conditions required for capturing and inspection from the design information and a scanning electron microscope system for actually performing capturing and inspection. Moreover, in the case of performing a matching process between designed data and a SEM image, deformed parts are corrected by use of edge information in accordance with multiple directions and smoothing thereof. Furthermore, a SEM image corresponding to a detected position is re-registered as a template, and the matching process is thereby performed.

Claims

1. A method of matching an image of a pattern on a semiconductor device produced by a semiconductor inspection system and a template comprising a bit map of CAD data, the method comprising the steps of:

decomposing the edges of the pattern image;

smoothing the edge-decomposed pattern image and the template; and

matching the smoothed pattern image and the template.

2. The method according to claim 1, wherein the template is smoothed more strongly than the pattern image is.

3. A method of matching an image of a pattern on a semiconductor device produced by a semiconductor inspection system and a template comprising a bit map of CAD data, the method comprising the steps of:

extracting the edges of the pattern image by breaking up the edges in a plurality of directions;

smoothing each of the images of the edges broken up in the multiple directions;

composing the smoothed edge images in the multiple directions; and

matching the composed pattern image and the template.

4. A computer program for an image processor for matching an image produced by a semiconductor inspection system and a template comprising a bit map of CAD data that is stored in advance, the computer program controlling the image processor such that the processor decomposes the edges of the image produced by the semiconductor inspection system, smoothes the edge-decomposed image and the template, and matches the smoothed image and the template.

5. An image processor controlled by the computer program of claim 4.

6. The computer program according to claim 4, wherein the image processor is controlled such that edges are extracted from the image in a plurality of directions, and the extracted edges in the multiple directions are composed prior to the matching process.

7. A semiconductor inspection system controlled by the computer program of claim 6.