Isolation circuit

• US 7,026,646 B2
• Filed: 06/20/2002
• Issued: 04/11/2006
• Est. Priority Date: 06/20/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Primary Examiner(s): Lohe, Steven
• Assistant Examiner(s): IM, JUNGHWA M
• Application Number:
  US10/176,015
• Publication Number:
  US 20030234393A1
• Time in Patent Office: 1,391 Days
• Field of Search: 257/48, 257/786, 257/620, 257/203, 257/678, 257/692, 438/17, 438/18, 438/462
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Claims

1. An isolation circuit for wafer-level testing, comprising:

a first probe pad located in the scribe area of a wafer and adapted to receive a first external control signal;

a second probe pad located in the scribe area and adapted to receive a second external control signal;

a part pad coupled to interior circuits of a microelectronic die and located in the interior area of the microelectronic die; and

an isolation device comprising a metal oxide semiconductor (MOS) transistor located in the scribe area and adapted to transfer the second external control signal from the second probe pad to the part pad in response to the first external control signal.

2. The isolation circuit of claim 1, wherein the isolation device is fabricated in the redistribution layer.

3. The isolation circuit of claim 1, further includes a second isolation device connected to the isolation device to selectively prevent the second probe pad from being coupled to the part pad.

4. The isolation circuit of claim 1, further includes a radio frequency identification (RFID) circuit connected to the first isolation device to selectively prevent the second probe pad from being coupled to the part pad.

5. The isolation circuit of claim 1, wherein each of the first pad, the second pad and the isolation device are respectively formed is fabricated in the redistribution, layer.

6. An isolation circuit far wafer-level testing, comprising:

a first test pad located in the scribe area of a wafer and adapted to receive control signals generated external to the wafer;

a second test pad located in the scribe area of a wafer and adapted to receive test signals generated external to the wafer;

a part pad coupled to a microelectronic die and located in the interior area of the microelectronic die;

a first device comprising a metal oxide semiconductor (MOS) transistor adapted to transfer the test signals from the second test pad to the part pad in response to a predetermined control signal; and

a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the microelectronic die.

7. The isolation circuit of claim 6, wherein the second device comprises at least one of a MOS device, a multiplexor circuit, a conductive jumper, a ball-bond, a fuse device or an anti-fuse device, and wherein the second device is adapted to inactivate the first device during the predetermined use of the microelectronic die.

8. The isolation circuit of claim 7, wherein the second device comprises a wireless identification circuit.

9. The isolation circuit of claim 6, wherein the first device comprises an N-channel transistor and the second device inactivates the N-channel transistor by coupling a gate of the N-channel transistor to ground potential.

10. The isolation circuit of claim 6, wherein the first device comprises a P-channel transistor and the second device inactivates the P-channel transistor by coupling a gate of the P-channel transistor to a high potential.

11. The isolation circuit of claim 6, further comprising a third device to selectively disconnect the first pad front the first device.

12. The isolation circuit of claim 6, further comprising a third device to selectively connect the first pad to the first device.

13. An isolation circuit located in a scribe area of a wafer and operable for assisting wafer-level testing comprising:

a gate control pad located in the scribe area and adapted to receive a control signal;

a plurality of test pads located in the scribe area and adapted to receive a test signal;

a plurality of part pads each coupled to a microelectronic die on the wafer;

a plurality of first devices located in the scribe area, each comprising a metal oxide semiconductor (MOS) transistor and each adapted to transfer the test signal from one of the plurality of test pads to a corresponding one of the plurality of part pads in response to the control signal; and

at least one second device to selectively prevent the test pad from being coupled to the part pad.

14. The isolation circuit of claim 13, wherein each of the plurality of first devices comprises an N-channel MOS transistor and the at least one second device inactivates each of the N-channel transistors by coupling a gate of each transistor to ground potential.

15. The isolation circuit of claim 13, wherein the at least one second device comprises one of a radio frequency (RF) identification circuit, and an N-channel transistor including a gate coupleable to a supply voltage during a selected use of the microelectronic die.

16. An isolation circuit located in a scribe area of a wafer, comprising:

a gate control pad located in the scribe area and adapted to receive a control signal;

a plurality of test pads located in the scribe area and adapted to receive a test signal;

a plurality of part pads each coupled to a microelectronic die;

a plurality of first devices each comprising at least one metal oxide semiconductor (MOS) transistor and, adapted to transfer the test signal from one of the plurality of test pads to a corresponding one of the plurality of part pads in response to the control signal;

at least one second device to selectively prevent the test pad from being coupled to the part pad; and

a plurality of third devices, each third device being adapted to selectively disconnect the gate control pad from each of the first devices.

17. The isolation circuit of claim 16, wherein each of the plurality of third devices comprises a wireless identification circuit.

18. The isolation circuit of claim 16, wherein the gate control pad, the plurality of test pads and the plurality of part pads are formed in a redistribution layer.

19. An isolation circuit for wafer-level testing comprising:

a plurality of test pads located in the scribe area of a wafer arid adapted to receive test signals;

a plurality of part pads each coupled to a microelectronic die;

a plurality of first metal oxide semiconductor fMOS) devices to couple each of the plurality of test pads to an associated one of the plurality of part pads in response to an enable signal;

an enable pad coupled to each of the first devices to receive the enable signal; and

a disable pad coupled to each of the first devices to receive a disable signal.

20. The isolation circuit of claim 19, further comprising;

a second device to connect or disconnect the enable pad from each of the first metal oxide semiconductor (MOS) devices; and

a third device to connect or disconnect the disable pad from each of the first devices.

21. The isolation circuit of claim 20, wherein the second device and third devices each comprise one of a conductive jumper and an anti-fuse device to respectively connect the enable pad and the disable pad to each of the first devices.

22. The isolation circuit of claim 20, wherein the second and third devices each comprise a fuse to respectively disconnect the enable pad and the disable pad from each of the first devices.

23. An isolation circuit for wafer-level testing comprising:

a first pad located in a scribe area of a wafer and adapted to receive a control signal;

a second pad located in a scribe area of a wafer and adapted to be coupled to a power source;

a third pad coupled to a microelectronic die; and

a metal oxide semiconductor (MOS) device adapted to couple the second pad to the third pad in response to the control signal during normal use of the microelectronic die.

24. A microelectronic die, comprising:

a first pad located in a scribe area of a wafer and adapted to receive a control signal;

a second pad located in the scribe area and adapted to receive another signal;

a third pad coupled to a component formed on the microelectronic die; and

a metal oxide semiconductor (MOS) device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

25. The microelectronic die of claim 24, further comprising a second device adapted to selectively prevent the second pad from being coupled to the third pad during a non-test use of the microelectronic die.

26. The microelectronic die of claim 25, wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

27. The microelectronic die of claim 24, wherein the MOS device comprises an N-channel MOS device.

28. The microelectronic die of claim 24, further comprising a redistribution layer, wherein the first, second and third pads are formed in the redistribution layer.

29. A semiconductor wafer, comprising:

a plurality of microelectronic dies on the semiconductor wafer and having scribe areas between the microelectronic dies; and

at least one isolation circuit associated with each microelectronic die, the at least one isolation circuit including;

a first probe pad located in the scribe areas and adapted to receive a control signal;

a second probe pad located in the scribe areas and adapted to receive a test signal;

a part pad coupled to the microelectronic die and located inside the die; and

a device comprising a metal oxide semiconductor (MOS) transistor located in the scribe area and adapted to transfer the test signal from the second probe pad to the part pad in response to the control signal.

30. The semiconductor wafer of claim 29, further comprising a second device adapted to selectively prevent the second probe pad from being coupled to the part pad during a predetermined use of the component.

31. The semiconductor wafer of claim 30, wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

32. An electronic system, comprising:

a processor; and

a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit on the microelectronic die and in scribe are as surrounding the microelectronic dies, the isolation circuit including;

a first probe pad located in the scribe areas and adapted to receive a control signal;

a second probe pad located in the scribe areas and adapted to receive a test signal;

a part pad coupled to the microelectronic die and located inside the die; and

a device comprising a metal oxide semiconductor (MOS) transistor located in the scribe area and adapted to transfer the test signal from the second probe pad to the part pad in response to the control signal.

33. The electronic system of claim 32, further comprising a second device adapted to selectively prevent the second probe pad from being coupled to the part pad during a predetermined use of the electronic system.