Versatile system for accelerated stress characterization of semiconductor device structures

• US 7,026,838 B2
• Filed: 06/18/2004
• Issued: 04/11/2006
• Est. Priority Date: 06/18/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Reddy, Vijay Kumar, Raha, Prasun
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/871,932
• Publication Number:
  US 20050280477A1
• Time in Patent Office: 662 Days
• Field of Search: None
• US Class Current: 324/762.08
• CPC Class Codes: G01R 31/275 for testing individual semiconductor components within integrated circuits
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.

Claims

1. Circuitry performing accelerated stress characterization of a given transistor, the circuitry comprising:

a plurality of inverter circuits, formed from the given transistor, disposed in series with one another;

a plurality of signal taps, each respectively and operatively associated with one gap between adjacent inverter circuits in the series thereof;

selective circuitry, operatively coupled to the plurality of signal taps and adapted to select a first and a second of the plurality of signal taps;

a controlled voltage component, operatively coupled the plurality of inverter circuits and adapted to supply a desired supply voltage thereto;

a controlled signal component, operatively coupled the plurality of inverter circuits and adapted to supply a signal of a desired frequency thereto; and

an evaluation component, adapted to receive signal data from the first and second signal taps.

2. The circuitry of claim 1, wherein plurality of inverter circuits disposed in series comprises at least eleven inverter circuits, and the plurality of signal taps comprise at least ten taps.

3. The circuitry of claim 1, wherein each gap between adjacent inverter circuits has a signal tap operatively coupled thereto.

4. The circuitry of claim 1, wherein each signal tap comprises an inverter circuit.

5. The circuitry of claim 1, wherein the selective circuitry comprises a multiplexer.

6. The circuitry of claim 1, wherein the controlled signal component comprises a constant frequency signal circuit.

7. The circuitry of claim 6, wherein the controlled signal component comprises a phase locked loop circuit.

8. The circuitry of claim 6, wherein the controlled signal component comprises a self-biasing frequency source circuit.

9. The circuitry of claim 6, wherein the controlled signal component comprises a ring oscillator circuit.

10. The circuitry of claim 6, wherein the ring oscillator circuit comprises:

an independent voltage supply;

a controllable current component driven by the independent voltage supply;

a single ring oscillator circuit driven by the controllable current component; and

a signal rectification component, driven by the independent voltage supply, receiving a signal from the single ring oscillator circuit, and outputting a rectified version of the signal from the single ring oscillator circuit.

11. The circuitry of claim 10, wherein the independent voltage supply is electrically isolated from the controlled voltage component.

12. The circuitry of claim 10, wherein the controllable current component comprises a current controlled current mirror.

13. The circuitry of claim 10, wherein the signal rectification component comprises a divide-by-two circuit.

14. A method of characterizing performance of a given transistor, the method comprising the steps of:

providing a plurality of inverter circuits, formed from the given transistor, disposed in series with one another;

providing a plurality of signal taps, each respectively and operatively associated with one gap between adjacent inverter circuits in the series thereof;

providing selective circuitry, operatively coupled to the plurality of signal taps and adapted to select a first and a second of the plurality of signal taps;

supplying a fixed frequency source signal to the plurality of inverter circuits;

supplying a first supply voltage to the plurality of inverter circuits;

compiling a first set of signal data from the first and second signal taps;

supplying a second supply voltage to the plurality of inverter circuits;

compiling a second set of signal data from the first and second signal taps; and

processing the first and second sets of signal data to determine a desired transistor performance characteristic.

15. The method of claim 14, wherein the step of providing selective circuitry further comprises providing a multiplexer.

16. The method of claim 14, wherein the step of providing a fixed frequency source signal further comprises providing a ring oscillator circuit.

17. The method of claim 16, wherein the step of providing a ring oscillator circuit further comprises:

providing an independent voltage supply;

providing a controllable current component driven by the independent voltage supply;

providing a single ring oscillator circuit driven by the controllable current component; and

providing a signal rectification component, driven by the independent voltage supply, receiving a signal from the single ring oscillator circuit, and outputting a rectified version of the signal from the single ring oscillator circuit.

18. The method of claim 17, wherein the step of providing a controllable current component comprises a current controlled current mirror.

19. The method of claim 17, wherein the step of providing a signal rectification component further comprises providing a divide-by-two circuit.

20. A semiconductor device characterization system comprising:

an evaluation structure, comprising an arrangement of one or more sample devices;

a first control component, operatively coupled to the evaluation structure and adapted to control a first operational parameter of the evaluation structure;

a second control component, operatively coupled to the evaluation structure and adapted to control a second operational parameter of the evaluation structure independent of any variance in the first operational parameter; and

an evaluation component, adapted to receive and compile data from the evaluation structure as either the first or second operational parameters are varied.