Time multiplexing bus for DTV common interface

• US 7,027,526 B1
• Filed: 03/01/2002
• Issued: 04/11/2006
• Est. Priority Date: 03/01/2002
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Zhao, Yuanping, Nehoran, Yoed I.
• Primary Examiner(s): TRAN, KHANH C
• Application Number:
  US10/087,111
• Time in Patent Office: 1,502 Days
• Field of Search: 375/257, 375/316, 375/377, 375/295, 348/552, 725/80, 725/100, 725/141, 725/139, 725/151, 725/153, 725/131, 725/133
• US Class Current: 375/316
• CPC Class Codes: H04N 21/40 Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof

Abstract

A device for use in a digital video receiver. The device generally comprising a demodulator circuit, a decoder circuit, a plurality of bi-directional buffers, and a circuit. The demodulator circuit may be configured to generate (i) a first clock signal compliant with a standard interface for the digital video receiver and (ii) a first plurality of data signals compliant with the standard interface. The decoder circuit may be configured to receive a second plurality of data signals compliant with the standard interface. The plurality of first bi-directional buffers may be configured to multiplex the first data signals with the second data signals at a plurality of data interfaces in response to the first clock signal. The circuit may be configured to generate a direction signal at a direction interface in response to the first clock signal to indicate a direction of the data interfaces.

Claims

1. A device comprising:

a demodulator circuit configured to generate (i) a first clock signal compliant with a standard interface for a digital video receiver and (ii) a first plurality of data signals compliant with said standard interface;

a decoder circuit configured to receive a second plurality of data signals compliant with said standard interface;

a plurality of first bi-directional buffers configured to multiplex said first data signals with said second data signals at a plurality of data interfaces in response to said first clock signal;

a circuit configured to generate a direction signal at a direction interface in response to said first clock signal to indicate a direction of said data interfaces; and

a delay circuit configured to generate a second clock signal compliant with said standard interface by phase shifting said first clock signal.

2. The device according to claim 1, wherein said second data signals are ready to be read at an edge of said second clock signal.

3. The device according to claim 1, wherein said delay circuit is further configured to generate a third clock signal compliant with said standard interface at a clock interface by phase shifting said first clock signal.

4. The device according to claim 3, wherein said first data signals are ready to be read at an edge of said third clock signal.

5. The device according to claim 1, further comprising a second bi-directional buffer configured to multiplex a first valid signal compliant with said standard interface with a second valid signal compliant with said standard interface at a valid interface in response to said first clock signal, said first valid signal indicating when said first data signals are valid and said second valid signal indicating when said second data signals are valid.

6. The device according to claim 5, further comprising a third bi-directional buffer configured to multiplex a first synchronization signal compliant with said standard interface with a second synchronization signal compliant with said standard interface at a synchronization interface in response to said first clock signal, said first synchronization signal indicating a first start of packet for said first data signal and said second synchronization signal indicating a second start of packet for said second data signals.

7. The device according to claim 1, wherein said demodulator circuit is further configured to generate an error signal at an error interface to indicate a demodulation error.

8. The device according to claim 7, further comprising:

wherein said second data signals are ready to be read at an edge of said second clock signal;

a second bi-directional buffer configured to multiplex a first valid signal compliant with said standard interface with a second valid signal compliant with said standard interface at a valid interface in response to said first clock signal, said first valid signal indicating when said first data signals are valid and said second valid signal indicating when said second data signals are valid; and

a third bi-directional buffer configured to multiplex a first synchronization signal compliant with said standard interface with a second synchronization signal compliant with said standard interface at a synchronization interface in response to said first clock signal, said first synchronization signal indicating a first start of packet for said first data signal and said second synchronization signal indicating a second start of packet for said second data signals.

9. The device according to claim 8, wherein said standard interface comprises European Standard reference number EN 50221.

10. A method of transferring data defined by a standard interface for a digital video receiver comprising the steps of:

(A) generating a first clock signal compliant with said standard interface;

(B) multiplexing a first plurality of data signals compliant with said standard interface with a second plurality of data signals compliant with said standard interface at a plurality of data interfaces in response to said first clock signal;

(C) generating a direction signal at a direction interface in response to said first clock signal to indicate a direction of said data interfaces; and

(D) generating a second clock signal compliant with said standard interface in response to chase shifting said first clock signal.

11. The method according to claim 10, wherein said second data signals are ready to be read at an edge of said second clock signal.

12. The method according to claim 10, further comprising the step of generating a third clock signal compliant with said standard interface at a clock interface in response to phase shifting said first clock signal.

13. The method according to claim 12, wherein said first data signals are ready to be read at an edge of said third clock signal.

14. The method according to claim 10, further comprising the step of multiplexing a first valid signal compliant with said standard interface with a second valid signal compliant with said standard interface, said first valid signal indicating when said first data signals are valid and said second valid signal indicating when said second data signals are valid.

15. The method according to claim 14, further comprising the step of multiplexing a first synchronization signal compliant with said standard interface with a second synchronization signal compliant with said standard interface in response to said first clock signal, said first synchronization signal indicating a first start of packet for said first data signal and said second synchronization signal indicating a second start of packet for said second data signals.

16. The method according to claim 10, further comprising the step of generating an error signal at an error interface to indicate a demodulation error.

17. A device comprising:

a demodulator circuit configured to generate (i) a first clock signal compliant with a standard interface for a digital video receiver and (ii) a first plurality of data signals compliant with said standard interface;

a decoder circuit configured to receive a second plurality of data signals compliant with said standard interface;

a plurality of first bi-directional buffers configured to multiplex said first data signals with said second data signals at a plurality of data interfaces in response to said first clock signal; and

a circuit configured to generate a direction signal at a direction interface in response to said first clock signal to indicate a direction of said data interfaces, wherein said demodulator circuit is further configured to generate an error signal at an error interface to indicate a demodulation error.