Shift register

• US 7,027,551 B2
• Filed: 06/29/2004
• Issued: 04/11/2006
• Est. Priority Date: 07/24/2003
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lim, Kyoung-Moon, Han, Sang-Soo
• Primary Examiner(s): Lam, Tuan T.
• Application Number:
  US10/878,305
• Publication Number:
  US 20050018807A1
• Time in Patent Office: 651 Days
• Field of Search: 345/99, 345/100, 377/69, 377/79
• US Class Current: 377/69
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A shift register having a simple configuration and improved response and power consumption is disclosed. In the shift register, a plurality of stages are connected to each other in cascade and scanned in a bilateral direction. In the stages, a charger charges a first supply voltage into a first node in response to a clock signal. A discharger discharges the first node in response to a first start pulse or a second start pulse. A scan direction controller is connected between the charger and the discharger to discharge the first node into a different path in response to a scan direction control signal. An output part outputs any one of said first and second supply voltages as an output signal in response to a voltage at the first node. A latch part latches said output signal using said output signal and a clock signal inverted from said clock signal to feed back the latched output signal to the first node.

Claims

1. A shift register having a plurality of stages connected to each other in cascade to be scanned in a bilateral direction, each of said plurality of stages comprising:

a charger that charges a first supply voltage into a first node in response to a clock signal;

a discharger that discharges the first node in response to a first start pulse or a second start pulse;

a scan direction controller connected between the charger and the discharger to discharge the first node into a different path in response to a scan direction control signal;

output means that outputs any one of said first and second supply voltages as an

output signal in response to a voltage at the first node; and

latch means that latches said output signal using said output signal and a clock signal inverted from said clock signal to feed back the latched output signal to the first node.

2. The shift register according to claim 1, wherein said charger comprises:

a first transistor that controls a conductive path between a supply line for said first supply voltage and the first node in response to said clock signal.

3. The shift register according to claim 2, wherein said discharger comprises:

a second transistor that controls a conductive path between the first node and the clock signal supply line in response to said first start pulse; and

a third transistor connected, in parallel, to the second transistor to control said conductive path in response to said second start pulse.

4. The shift register according to claim 3, wherein said scan direction controller comprises:

a fourth transistor for controlling a conductive path between the first node and the second transistor in response to a first direction control signal; and

a fifth transistor for controlling a conductive path between the first node and the third transistor in response to a second direction control signal.

5. The shift register according to claim 4, wherein said first start pulse is a forward start pulse in which an output signal of the previous stage is input, and said second start pulse is a backward start pulse in which an output signal of the previous stage is input.

6. The shift register according to claim 5, wherein said first direction control signal has a logical state opposite to said second direction control signal.

7. The shift register according to claim 5, wherein said fourth transistor forms a discharge path between the first node and the second transistor when the plurality of stages is scanned forward, and said fifth transistor forms a discharge path between the first node and the third transistor when the plurality of stages is scanned backward.

8. The shift register according to claim 4, wherein said output means includes:

an inverter for inverting a voltage at the first node.

9. The shift register according to claim 8, wherein said inverter comprises:

a sixth transistor for controlling a conductive path between a supply line for said first supply voltage and an output line of the stage in response to a voltage at a node; and

a seventh transistor for controlling a conductive path between a supply line for said second supply voltage and said output line of the stage in opposition to the sixth transistor in response to said voltage at the node.

10. The shift register according to claim 9, wherein said latch means inverts and latches said output signal to feed it back into the first node.

11. The shift register according to claim 9, wherein said latch means comprises:

an eighth transistor for controlling a conductive path between said supply line for said first supply voltage and the first node in response to said output signal;

a ninth transistor for controlling a conductive path between said supply line for said second supply voltage and the first node in response to said output signal;

a tenth transistor for controlling a conductive path between said supply line for said first supply voltage and the eighth transistor in response to said inverted clock signal; and

an eleventh transistor for controlling a conductive path between said supply line for said second supply voltage and the ninth transistor in response to said clock signal.

12. The shift register according to claim 11, wherein said tenth transistor is turned on or off simultaneously with the eighth transistor, and said eleventh transistor is turned on or off simultaneously with the ninth transistor.

13. The shift register according to claim 9, wherein said second, third, fourth, fifth, seventh, ninth and eleventh transistors have polarity characteristics opposite to said first, sixth, eighth and tenth transistors.

14. The shift register according to claim 1, wherein said first supply voltage is larger than said second supply voltage.

15. The shift register according to claim 1, wherein odd stages of said plurality of stages use a first clock and an inverted first clock signal while even stages of said plurality of stages use a second clock and an inverted second clock signal.

16. The shift register according to claim 15, wherein said first clock signal has a phase difference of ¼

period from said second clock signal.

17. The shift register according to claim 16, wherein an output signal of each of said plurality of stages partially overlaps with an output signal of the previous stage.