Processing architecture having a compare capability

• US 7,028,170 B2
• Filed: 03/08/2001
• Issued: 04/11/2006
• Est. Priority Date: 03/08/2000
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Saulsbury, Ashley
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): Li, Aimee J.
• Application Number:
  US09/802,291
• Publication Number:
  US 20020019928A1
• Time in Patent Office: 1,860 Days
• Field of Search: 712/222, 712/223, 712/224
• US Class Current: 712/223
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

According to the invention, a processing core that executes a compare instruction is disclosed. The processing core includes a register file, comparison logic, decode logic, and a store path. Included in the register file are a number of general-purpose registers. The general-purpose registers include a first input operand register, a second input operand register and an output operand register. Comparison logic is coupled to the register file. The comparison logic tests for at least two of the following relationships: less than, equal to, greater than and no valid relationship. The decode logic selects the output operand register from the plurality of general-purpose registers. The store path extends between the comparison logic and the selected output operand register.

Claims

1. A processing core that executes a compare instruction, the processing core comprising:

a plurality of general-purpose registers comprising a first input operand register, a second input operand register and an output operand register;

a register file comprising the plurality of general-purpose registers;

comparison logic coupled to the register file, wherein;

the comparison logic tests for at least two of a following relationships with the compare instruction alone;

less than, equal to, greater than or no valid relationship,

the comparison logic with the compare instruction alone produces a value, and

the value has at least four states to represent the at least two relationships;

decode logic, which selects the output operand register from the plurality of general-purpose registers; and

a store path between the comparison logic and the selected output operand register, wherein the value is stored in the selected output operand register,

wherein the compare instruction comprises a machine code instruction.

2. The processing core that executes the compare instruction as set forth in claim 1, wherein a very long instruction word includes a plurality of compare instructions.

3. The processing core that executes the compare instruction as set forth in claim 1, wherein said decode logic selects the first and second input operand registers from the plurality of general-purpose registers.

4. The processing core that executes the compare instruction as set forth in claim 1, wherein the processing core issues a plurality of compare instructions at one time.

5. The processing core that executes the compare instruction as set forth in claim 1, further comprising:

a first load path between the first input operand register and the comparison logic; and

a second load path between the second input operand register and the comparison logic.

6. The processing core that executes the compare instruction as set forth in claim 1, wherein the value is an integer.

7. The processing core that executes the compare instruction as set forth in claim 1, wherein:

the first input operand register is a double precision floating point data type;

the second input operand register is a single precision floating point data type; and

the output operand register is a double precision floating point data type.

8. The processing core that executes the compare instruction as set forth in claim 1, further comprising a plurality of processing paths that are coupled to the register file.

9. The processing core that executes the compare instruction as set forth in claim 1, wherein the register file comprises special purpose registers which cannot store an output operand.

10. The processing core that executes the compare instruction as set forth in claim 1, wherein the value in the operand register can be written to a location outside of the processing core.

11. A method for performing a compare operation, the method comprising steps of:

receiving a compare instruction comprising a machine code instruction;

configuring first and second paths between a register file and comparison logic;

configuring a third path between the comparison logic and the register file;

comparing a first input operand and a second input operand with the compare operation alone, wherein the comparing step comprises step of;

producing a result, which has at least four states to indicate at least two of a following mathematical relationships between the first input operand and the second input operand;

less than, equal to, greater than, or no valid relationship; and

coupling the result to a general-purpose register in the register file.

12. The method for performing the compare operation as set forth in claim 11, the method further comprising a step of enabling the comparison logic in an arithmetic logic unit.

13. The method for performing the compare operation as set forth in claim 11, wherein the configuring steps each comprise a step of addressing a general-purpose register in the register file.

14. The method for performing the compare operation as set forth in claim 11, wherein a compare operation is comprised within a very long instruction word.

15. The method for performing the compare operation as set forth in claim 11, wherein the comparing step comprises a step of converting a data type of at least one of the first or second input operands.

16. The method for performing the compare operation as set forth in claim 11, wherein the result can be written to a location outside of the processing core.

17. A method for executing a compare instruction in a processor, the method comprising steps of:

issuing the compare instruction comprising a machine code instruction;

comparing a first input operand and a second input operand to determine at least two mathematical relationships between the first and second input operands, wherein the compare instruction alone causes the comparing step;

determining an output operand which has at least four states indicative of the at least two mathematical relationships; and

storing the output operand in a general-purpose register of a register file, wherein the output operand alone indicates the at least two mathematical relationships between the first and second input operands.

18. The method for executing the compare instruction in the processor as set forth in claim 17, wherein the comparing step comprises at least two of the following steps:

determining if the first input operand is less than the second input operand;

determining if the first input operand is greater than the second input operand;

determining if the first input operand is equal to the second input operand;

or

determining if there is no valid relationship between the first input operand and the second input operand.

19. The method for executing the compare instruction in the processor as set forth in claim 17, wherein the compare instruction is a very long instruction word which comprises a plurality of compare instructions which are processed in parallel down separate processing paths.

20. The method for executing the compare instruction in the processor as set forth in claim 17, wherein the general-purpose register is used to store operators from other types of instructions.