Error indication in a raid memory system

• US 7,028,213 B2
• Filed: 09/28/2001
• Issued: 04/11/2006
• Est. Priority Date: 09/28/2001
• Status: Expired due to Term

• Current Assignee: Nera Innovations Limited (Atlantic IP Services Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Tavallaei, Siamak, Autor, Jeffrey S., Ferguson, Patrick L., Galloway, Jeffery, Johnson, Jerome J., Piccirillo, Gary J., Majni, Tim, Lester, Robert A., Fink, Dan, Roscoe, Bret D., Post, Christian H., Clark, Benjamin H., MacLaren, John M., Larson, John E.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): DUNCAN, MARC M
• Application Number:
  US09/965,883
• Publication Number:
  US 20030088805A1
• Time in Patent Office: 1,656 Days
• Field of Search: 714/42, 714/5, 714/8, 714/47
• US Class Current: 714/5.1
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/328 Computer systems status display G06F11/327 takes precedence
• CPC Class Codes: G06F 2211/1052 RAID padding, i.e. completing a redundancy group with dummy data

Abstract

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Claims

1. A system comprising:

a host/data controller; and

a memory system comprising a plurality of memory cartridges operably coupled to the host/data controller, each memory cartridge comprising an operation indicator configured to indicate the operational status of the corresponding memory cartridge, wherein the operation indicator comprises a bit having a first state and a second state, the first state indicating that the memory cartridge is operational and the second state indicating that the memory cartridge is not operational, wherein the memory system is configured to operate in a redundant mode when each of the bits is in the first state, wherein at least one of the host/data controller and the plurality of memory cartridges comprise error detection components, and wherein the host/data controller is configured to generate a low priority interrupt signal in response to error detection by the error detection components if each of the operation bits is in the first state.

2. The system, as set forth in claim 1, wherein the memory system comprises a redundant memory system.

3. The system, as set forth in claim 2, wherein the memory system comprises five memory cartridges.

4. The system, as set forth in claim 1, wherein the host/data controller is configured to generate a low priority interrupt signal in response to multi-bit error detection by the error detection components if each of the operation bits is in the first state.

6. The system, as set forth in claim 1, wherein each of the plurality of memory cartridges comprises a plurality of memory devices.

5. A system comprising:

a host/data controller; and

a memory system comprising a plurality of memory cartridges operably coupled to the host/data controller, each memory cartridge comprising an operation indicator configured to indicate the operational status of the corresponding memory cartridge, wherein the operation indicator comprises a bit having a first state and a second state, the first state indicating that the memory cartridge is operational and the second state indicating that the memory cartridge is not operational, wherein the memory system is configured to operate in a redundant mode when each of the bits is in the first state, wherein at least one of the host/data controller and the plurality of memory cartridges comprise error detection components, and wherein the host/data controller is configured to generate a high priority interrupt signal in response to multi-bit error detection if at least one of the operation bits is in the second state.

7. The system, as set forth in claim 5, wherein the memory system comprises a redundant memory system.

8. The system, as set forth in claim 5, wherein the memory system comprises five memory cartridges.

9. The system, as set forth in claim 5, wherein each of the plurality of memory cartridges comprises a plurality of memory devices.

10. A method of generating interrupts in a redundant memory, comprising the acts of:

detecting an error in a memory system;

determining the operational status of the memory system, wherein the act of determining the operational status comprises reading five operation bits, each of the operation bits indicating the operational status of a corresponding segment of the memory, the operational status comprising one of an operational state and a non-operational state; and

initiating a system interrupt signal, the type of system interrupt signal being dependent on the operational status of the memory system, wherein the act of initiating a system interrupt comprises the act of initiating a low priority system interrupt if each of the five operation bits is in the operational state.

11. The method, as set forth in claim 10, wherein the act of detecting an error comprises the act of detecting a multi-bit error.

12. The method, as set forth in claim 10, wherein the act of determining the operational status comprises the act of determining whether the system is operating in one of a redundant mode and a non-redundant mode.

13. A method of generating interrupts in a redundant memory, comprising the acts of:

detecting an error in a memory system;

determining the operational status of the memory system, wherein the act of determining the operational status comprises reading five operation bits, each of the operation bits indicating the operational status of a corresponding segment of the memory, the operational status comprising one of an operational state and a non-operational state; and

initiating a system interrupt signal, the type of system interrupt signal being dependent on the operational status of the memory system, wherein the act of initiating a system interrupt comprises the act of initiating a high priority system interrupt if any of the five operation bits is in the non-operational state.

14. The method, as set forth in claim 13, wherein the act of detecting an error comprises the act of detecting a multi-bit error.

15. The method, as set forth in claim 13, wherein the act of determining the operational status comprises the act of determining whether the system is operating in one of a redundant mode and a non-redundant mode.

16. A system comprising:

a memory cartridge comprising an operation indicator configured to indicate an operational status of the memory cartridge; and

a controller operably coupled to the memory cartridge and configured to generate a low priority interrupt if an error detection component detects a memory error and the memory cartridge is operational.

17. The system, as set forth in claim 16, wherein the operation indicator comprises a bit having a first state and a second state, the first state indicating that the memory cartridge is operational and the second state indicating that the memory cartridge is not operational.

18. The system, as set forth in claim 17, comprising a memory system comprising a plurality of the memory cartridges.

19. The system, as set forth in claim 18, wherein the memory system is configured to operate in a redundant mode when the bits within each of the plurality of memory cartridges are in the first state.

20. The system, as set forth in claim 16, wherein the controller is configured to generate a low priority interrupt signal if the error detection component detects a multi-bit error when the memory cartridge is operational.

21. The system, as set forth in claim 16, wherein the controller is configured to generate a high priority interrupt signal if the error detection component detects a multi-bit error when the memory cartridge is not operational.

22. The system, as set forth in claim 21, wherein the high priority interrupt signal comprises a non-maskable interrupt (NMI).

23. The system, as set forth in claim 16, wherein the controller comprises the error detection component.

24. The system, as set forth in claim 16, wherein the memory cartridge comprises a plurality of memory devices.

25. A method comprising:

detecting an error in a memory system;

determining whether the system is operating in a redundant mode or in a non-redundant mode; and

initiating a low priority system interrupt signal if the memory system is operating in the redundant mode.

26. The method, as set forth in claim 25, comprising initiating a high priority system interrupt if the memory system is operating in a non-redundant mode.

27. The method, as set forth in claim 26, wherein initiating the high priority system interrupt comprises initiating a non-maskable interrupt (NMI).

28. The method, as set forth in claim 25, wherein detecting the error comprises detecting a multi-bit error.

29. The method, as set forth in claim 25, wherein detecting an error in a memory system comprises detecting an error on a memory cartridge comprising a plurality of memory devices.

30. The method, as set forth in claim 25, wherein determining whether the system is operating in either a redundant mode or a non-redundant mode comprises reading a plurality of operation bits, wherein each of the operation bits indicates the operating mode of a segment of the memory system.

31. The method, as set forth in claim 30, wherein determining the operating mode comprises reading five operation bits.

32. The method, as set forth in claim 31, wherein initiating a low priority system interrupt signal comprises initiating the low priority system interrupt if each of the five operation bits is in an operational state.

33. The method, as set forth in claim 31, comprising initiating a high priority system interrupt if any of the five operation bits is in a non-operational state.