Error correction code circuit with reduced hardware complexity

• US 7,028,247 B2
• Filed: 12/25/2002
• Issued: 04/11/2006
• Est. Priority Date: 12/25/2002
• Status: Expired due to Fees

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Faraday Technology Corp.
• Inventors: Lee, Heng-Kuan
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US10/248,188
• Publication Number:
  US 20040153722A1
• Time in Patent Office: 1,203 Days
• Field of Search: 714/784
• US Class Current: 714/784
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10
• CPC Class Codes: H03M 13/158 Finite field arithmetic processing

Abstract

An error correction code circuit with reduced hardware complexity is positioned inside a microprocessor. The microprocessor has a Galois field multiplier for performing a Galois field multiplication on data processed by the error correction code circuit. The error correction code circuit has a first register for storing an input data, a plurality of calculation units, a third register for storing an output data corresponding to the input data, and a controller for controlling operation of the error correction code circuit. Each calculation unit has a Galois field adder, and a second register electrically connected to the Galois field adder. The controller transmits data of each calculation unit to the same Galois field multiplier for a corresponding Galois field multiplication, and the result outputted by the Galois field multiplier is transmitted back to the error correction code circuit.

Claims

1. A processing circuit of a microprocessor for processing an input data to generate an output data, the microprocessor comprising a Galois field multiplier electrically connected to the processing circuit for, performing a Galois field multiplication upon a plurality of processing data being processed by the processing circuit, the processing circuit comprising:

a first register for storing the input data;

a plurality of processing units each being cascaded in series, a starting processing unit of the processing units electrically connected to the first register, each processing unit comprising an input port, an output port, a Galois field adder electrically connected between the input port and the output port, and a second register electrically connected to the Galois field adder; and

a controller for controlling operation of the processing circuit;

wherein the controller controls each processing unit to transmit processing data requiring Galois field multiplication to the Galois field multiplier, and the processing data outputted from the Galois field multiplier are transmitted back to each corresponding processing unit.

2. The processing circuit of claim 1 wherein the Galois field adder performs an exclusive OR (XOR) logic operation.

3. The processing circuit of claim 1 wherein the Galois field multiplier is implemented by a hardware circuit or a software look-up table.

4. The processing circuit of claim 1 wherein the microprocessor is a digital signal processor (DSP).

5. The processing circuit of claim 1 further comprising a third register electrically connected to a terminal processing unit of the processing units for storing the output data.

6. The processing circuit of claim 1 wherein the microprocessor is used for processing a Reed-Solomon error correction code that has a plurality of symbols.

7. The processing circuit of claim 6 wherein the controller decides a total number of the processing units that are enabled according to a total number of the symbols of the Reed-Solomon error correction code.

8. The processing circuit of claim 1 wherein the processing unit further comprises:

a first switch positioned between the second register and the Galois field adder for controlling whether the Galois field adder is connected to the second register or not; and

a second switch for controlling whether the Galois field adder is electrically connected to the Galois field adder of an adjacent processing unit or the Galois field adder is electrically connected to a data transmission line.

9. The processing circuit of claim 8 wherein the processing circuit is used for generating a Reed-Solomon error correction code corresponding to the input data when the first switch makes the Galois field adder electrically connected to the second register and the second switch makes the Galois field adders of two adjacent processing units electrically connected.

10. The processing circuit of claim 9 further comprising a buffer electrically connected between two adjacent processing units, the output data of a leading processing unit of the two adjacent processing units being the input data of a following processing unit of the two adjacent processing units, wherein after the leading processing unit finishes processing a first input data and stores a corresponding first output data in the buffer, the leading processing unit is capable of handling a second input data to generate a corresponding second output data.

11. The processing circuit of claim 9 wherein the processing circuit is used for generating a syndrome code corresponding to the output data comprising the Reed-Solomon error correction code when the first switch makes the Galois field adder electrically disconnected from the second register and the second switch makes the Galois field adder electrically connected to the data transmission line.

12. The processing circuit of claim 11 wherein the processing circuit is used for determining an error location of the output data according to the syndrome code when the first switch makes the Galois field adder electrically disconnected from the second register and the second switch makes the Galois field adders of two adjacent processing units electrically connected.

13. A data processing method of a microprocessor, the microprocessor comprising:

a processing circuit for processing an input data to generate an output data, the processing circuit comprising;

a first register for storing the input data;

a plurality of processing units each being cascaded, a beginning processing unit of the processing units electrically connected to the first register, each processing unit comprising an input port, an output port, a Galois field adder electrically connected between the input port and the output port, and a second register electrically connected to the Galois field adder; and

a controller for controlling operation of the processing circuit; and

a Galois field multiplier electrically connected to the processing circuit for performing Galois field multiplication upon a plurality of processing data handled by the processing circuit;

the data processing method comprising;

controlling each processing unit to transmit processing data required the Galois field multiplication to the Galois field multiplier, and transmitting the processing data outputted from the Galois field multiplier back to each corresponding processing unit.

14. The data processing method of claim 13 wherein the Galois field adder performs an exclusive OR (XOR) logic operation.

17. The data processing method of claim 13 wherein the processing circuit further comprises a third register electrically connected to a terminal processing unit of the processing units for storing the output data.

15. The data processing method of claim 15 wherein the microprocessor is used for processing a Reed-Solomon error correction code that has a plurality of symbols.

16. The data processing method of claim 15 wherein the controller decides a total number of the processing units that are enabled according to a total number of the symbols of the Reed-Solomon error correction code.