FPGA with register-intensive architecture

• US 7,028,281 B1
• Filed: 07/12/2002
• Issued: 04/11/2006
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Agrawal, Om P., Sharpe-Geisler, Bradley A.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/194,771
• Time in Patent Office: 1,369 Days
• Field of Search: 716/1, 716/6, 716/12, 716/17, 716/18, 326/41
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

Field programmable gate arrays (FPGA'"'"'s) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT'"'"'s) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL'"'"'s) and/or block-intra-connect lines (e.g., FB'"'"'s) to the base LUT'"'"'s and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM'"'"'s for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA'"'"'s.

Claims

1. A field programmable gate array (FPGA) comprising:

(a) a plurality of substantially same logic blocks each having plural programmable lookup tables;

(b) for each of said lookup tables, at least two corresponding state-storing registers;

(c) within each logic block and for each of said lookup tables of the logic block, an internal-routing circuit that is programmable to route a result signal of the respective lookup table as a register input signal to at least one of the corresponding state-storing registers so that each of the state-storing registers can output a register-output signal that defines a registered or latched version of the register-input signal; and

(c1) a programmable input switch adapted to acquire a multi-bit dynamic write-enable steering signal for dynamically steering a write enable signal to a single-port or multi-port memory array overlapping with two or more of the lookup tables of the corresponding logic block.

2. The FPGA of claim 1 and further comprising:

(d) within each logic block and for each respective state-storing register, a programmable register-bypass multiplexer coupled to selectively output at least one of said register-input signal and register-output signal.

3. The FPGA of claim 2 and further comprising:

(e) for each given logic block, a corresponding programmable input switch adapted to selectively acquire signals from logic-blocks interconnecting lines and/or logic-block intra-connect lines adjacent to the given logic block, where the input switching switch is further operatively coupled to the lookup tables of the given logic block for programmably routing acquired signals to the lookup tables; and

(f) within each logic block and for each respective lookup table, a feedthrough line, operatively coupled between the input switch and the corresponding internal-routing circuit for routing at least one of the acquired signals from the input switch directly to the internal-routing circuit.

4. The FPGA of claim 3 and further wherein:

(e.1) for each respective lookup table in a given logic block, the corresponding programmable input switch includes at least one primary matrix output line whose acquired signal propagates directly into the respective feedthrough line without also propagating directly to an input-term signal-receiving terminal of the respective lookup table.

5. The FPGA of claim 4 and further wherein:

(e.2) an acquired signal which propagates directly into the feedthrough line of a corresponding lookup table for selective passage through the internal-routing circuit can also serve as at least one of;

(e.2a) a dynamic selection signal for carrying out at least one of, a 2;

1 dynamic selection function;

a 4;

1 dynamic selection function; and

a 5;

1 dynamic selection function;

(e.2b) a shift signal which can be shift-wise delayed by a shift-length determinable by input term signals supplied to the corresponding lookup table;

(e.2c) a memory input data signal for application to a write-data input terminal of a single-port or multi-port memory array overlapping with one or more of the lookup tables of the corresponding logic block; and

(e.2d) a dynamic write-enable steering signal for dynamically steering a write enable signal to a single-port or multi-port memory array overlapping with one or more of the lookup tables of the corresponding logic block.

6. The FPGA of claim 4 and further wherein:

(e.2) an acquired signal, which respectively propagates directly into the feedthrough lines of respective lookup tables for selective passage through the corresponding internal-routing circuits of those respective lookup tables, can also serve as a multi-bit dynamic selection signal for carrying out within the corresponding logic block at least one of;

a 4;

1 dynamic selection function and a 5;

1 dynamic selection function.

7. The FPGA of claim 3 and further wherein:

(e.1) said corresponding programmable input switch of each given logic block includes a first input switching matrix stage (ISM-1 stage) and a second input switching matrix stage (ISM-2 stage), where the ISM-2 stage is coupled to receive first stage signals that have been selectively transmitted through the ISM-1 stage and to further selectively transmit all or a subset of the first stage signals to the corresponding logic block.

8. The FPGA of claim 7 and further wherein:

(e.2) said second input switching matrix stage (ISM-2 stage) includes selective signal transmission circuit for selectively transmitting a same first stage signal simultaneously to two or more of the lookup tables in the given logic block.

9. The FPGA of claim 7 and further wherein:

(e.2) said second input switching matrix stage (ISM-2 stage) includes selective signal transmission circuit for selectively transmitting a same first stage signal to one, or simultaneously to all of the lookup tables in the given logic block.

10. The FPGA of claim 7 and further wherein:

(e.2) said first input switching matrix stage (ISM-1 stage) includes selective signal transmission circuit for selectively transmitting a same first stage signal to at least four different multiplexer output lines of the ISM-2 stage.

11. A field programmable gate any (FPGA) comprising:

(a) a plurality of logic blocks each having plural programmable lookup table, where each lookup table has me ability to directly implement a truth table for, and output a corresponding result signal representing, any Boolean function of at least 4 input term signals that are programmably routable to the lookup table;

(b) for each of said lookup table, at least two corresponding state-storing registers;

(c) within each logic block and for at least one of said lookup tables of the logic block, an internal-routing circuit that is programmable to route the result signal of a lookup table as a register input signal to at least one of the corresponding state storing registers of the lookup table; and

(c1) a programmable input switch adapted to acquire a multi-bit dynamic write-enable steering signal for dynamically steering a write enable signal to a single-port or multi-port memory array overlapping with two or more of the lookup tables of the corresponding logic block.

12. A field programmable gate array (FPGA) comprising:

(a) a plurality of logic blocks each having plural programmable lookup tables;

(b) for each of said lookup tables, at least two corresponding state-storing registers;

(c) within each logic block and for at least one of said lookup tables, an internal-routing circuit that is programmable to route the result signal of a lookup table as a register input signal to at least one of the corresponding state-storing registers of the lookup table;

(d) within each logic block and for each state-storing register, a programmable register-bypass multiplexer coupled to selectively output at least one of said register-input signal and register-output signal;

(e) for each logic block, a corresponding programmable input switch adapted to selectively acquire signals from logic-blocks interconnecting lines and/or logic-block intra-connect lines adjacent to the logic block, where the input switching switch is further operatively coupled to the lookup tables of the logic block;

(f) within each logic block and for each lookup table, a feedthrough line operatively coupled between the input switch and the corresponding internal-routing circuit for routing at least one of the acquired signals from the input switch directly to the internal-routing circuit;

(g) for each lookup table, the corresponding programmable input switch includes at least one primary matrix output line whose acquired signal propagates directly into the respective feedthrough line without also propagating directly to an input-term signal-receiving terminal of the respective lookup tale; and

(f) wherein at least two acquired signals which respectively propagate directly into the feedthrough lines of respective lookup tables for selective passage through the corresponding internal-routing circuits of those respective lookup tables, can also serve as respective at least ones of;

a multi-bit dynamic selection signal for carrying out within the corresponding logic block at least one of;

a 4;

1 dynamic selection function; and

a 5;

1 dynamic selection function; and

a multi-bit dynamic write-enable steering signal for dynamically steering a write enable signal to a single-port or multi-port memory array overlapping with two or more of the lookup tables of the corresponding logic block.