System and method of scalable transaction processing

• US 7,028,297 B2
• Filed: 05/05/2003
• Issued: 04/11/2006
• Est. Priority Date: 11/17/2000
• Status: Expired due to Fees

• Current Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Original Assignee: Aristos Logic Corp. (Steel Partners Holdings LP)
• Inventors: Horn, Robert L., Wilkins, Virgil V., Myran, Mark D., Walls, David S., Elumalai, Gnanashanmugam
• Primary Examiner(s): An, Meng-Al T.
• Assistant Examiner(s): Ali, Syed J
• Application Number:
  US10/429,048
• Publication Number:
  US 20030195918A1
• Time in Patent Office: 1,072 Days
• Field of Search: 718/100, 718/102, 718104-196, 709200-203, 707 1- 2, 707/100
• US Class Current: 718/100
• CPC Class Codes: G06F 2209/548 Queue
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: Y10S 707/99931 Database or file accessing

Abstract

A transaction processor pipeline architecture and associated apparatus for processing multiple queued transaction requests incorporates multiple processing elements working in parallel. Each processing element is configured to perform a specific function within the transaction processor system. Certain processing elements are assigned as function controllers, which are assigned to process specific transaction request subtask categories and may be augmented with dedicated hardware to accelerate certain subtask functions. Other processing elements are configured as list managers, which are optimized for managing data structure operations in memory. The processing elements are connected by a cross-point interconnect. The transaction processor system is configurable and scalable based on application needs.

Claims

1. A method for processing transactions in a system having N function controllers, the method comprising:

receiving a plurality of transactions, wherein each transaction comprises a plurality of subtasks, and each of the plurality of subtasks comprises a plurality of data structure operations for manipulating memory contents and a plurality of compute operations for performing processing;

assigning to each of said N function controllers, a different one of said plurality of subtasks from said plurality of transactions;

executing the plurality of compute operations, wherein the executing is performed by the N function controllers; and

sending the plurality of data structure operations to a plurality of list managers in a request for execution of the plurality of data structure operations, each of the plurality of list managers configured to act on an exclusive plurality of data structures contained within a plurality of memories.

2. The method of claim 1, wherein the system is a cache, and cache data and status information are stored in the plurality of memories, and the plurality of transactions are read or write requests for another memory device.

3. The method of claim 1, wherein each of said N function controllers is responsible for performing a specific category of subtask.

4. The method of claim 1, wherein none of said N function controllers owns any particular storage volume or is responsible for executing operations on units of data within said particular storage volume.

5. The method of claim 1, wherein each of the plurality of list managers is configured to communicate with each of the N function controllers and each of the plurality of memories.

6. The method of claim 1, wherein no communication occurs between the plurality of list managers.

7. The method of claim 1, wherein no communication occurs between the N function controllers.

8. The method of claim 1, wherein the plurality of list managers process only one request at a time.

9. The method of claim 1, wherein the requests do not include semaphores.

10. A scalable system for processing a plurality of transactions, comprising:

a plurality of function controllers;

a memory subsystem, comprising;

at least one memory for storing data structures; and

at least one list manager for manipulating the contents of said memory; and

an interconnect, coupling said plurality of function controllers with said memory subsystem;

wherein

each of said plurality of transactions comprise a plurality of subtasks, each subtask comprising a plurality of compute operations and a plurality of data structure operations for manipulating the contents of said memory subsystem, said plurality of subtasks from said plurality of transactions are assigned to different ones of said plurality of function controllers for execution;

each function controller executes the plurality of compute operations from the subtask assigned from the plurality of subtasks; and

each function controller sends at least one request to execute the plurality of data structure operations from the subtask assigned from the plurality of subtasks, the requests sent to the list manager associated with the data structure to be manipulated by the execution of the plurality of data structure operations.

11. The system of claim 10, wherein said at least one memory is a single memory and said at least one list manager is a single list manager coupled to said single memory for manipulating the contents of said single memory.

12. The system of claim 10, wherein said memory subsystem comprises N memories, and each one of said list managers is coupled to at least one of said N memories for manipulating the contents of said at least one of said N memories, wherein N is an integer greater than 1.

13. The system of claim 12, wherein said interconnect is a packet switch.

14. The system of claim 13, wherein said packet switch is a multi-channel packet switch.

15. The system of claim 12, wherein said interconnect is a shared memory.

16. The system of claim 12, wherein each of said function controllers is a general purpose processor.

17. The system of claim 12, wherein each of said function controllers includes at least one application specific processor.

18. The system of claim 17, wherein said at least one application specific processor includes a host interface controller.

19. The system of claim 17, wherein said at least one application specific processor includes a command decoder.

20. The system of claim 17, wherein said at least one application specific processor includes a cache controller.

21. The system of claim 10, wherein each of said plurality of function controllers is responsible for performing a specific category of subtask.

22. The system of claim 10, wherein the list managers are not configured to communicate with each other.

23. The system of claim 10, wherein the function controllers are not configured to communicate with each other.

24. The system of claim 10, wherein the at least one request does not include semaphores.