Dual-gate structure and method of fabricating integrated circuits having dual-gate structures
First Claim
1. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:
- forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;
forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer;
etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and
forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.
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Abstract
A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
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Citations
35 Claims
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1. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:
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forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing an integrated circuit device, comprising the following steps:
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forming a first high-K dielectric layer in a first area defined for a first gate structure of a first device and in a second area defined for a second gate structure of a second device; processing said first high-K dielectric layer to lower an etch rate to an etchant of said first high-K dielectric layer; forming a second high-K dielectric layer in said first and second areas over said first high-K dielectric layer, said first high-K dielectric layer having a lower etch rate to said etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:
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forming a first dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second dielectric layer in said first and second areas, said first dielectric layer having a lower etch rate to an etchant relative to said second dielectric layer; etching said second dielectric layer from said second area to said first dielectric layer wit said etchant; and forming a gate conductive layer in said first and second areas over said second dielectric layer and first dielectric layer, respectively, wherein said first dielectric layer is a high-K dielectric layer and said second dielectric layer is a non high-K dielectric layer, and wherein said first and second areas comprise channel areas having the same conductivity.
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19. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:
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forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; forming an interfacial layer between said substrate and said first high-K dielectric layer in said first and second areas; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:
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forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer after said etching step; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively. - View Dependent Claims (31, 32, 33, 34, 35)
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Specification