Dual-gate structure and method of fabricating integrated circuits having dual-gate structures

• US 7,030,024 B2
• Filed: 08/23/2002
• Issued: 04/18/2006
• Est. Priority Date: 08/23/2002
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yao, Liang-Gi, Chen, Chi-Chun, Yang, Chih-Wei, Chen, Chih-Chang, Wang, Ming-Fang, Ho, Tuo-Hung
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): Tran, Binh X.
• Application Number:
  US10/226,617
• Publication Number:
  US 20040038538A1
• Time in Patent Office: 1,334 Days
• Field of Search: 438/694, 438/699, 438/702, 438/704, 438/745, 438/751
• US Class Current: 438/702
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Claims

1. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;

forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer;

etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and

forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.

2. The method of claim 1,

wherein said first high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said second gate structure, and

wherein said second high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said first gate structure minus said target thickness for said gate dielectric for said second gate structure.

3. The method of claim 1, wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.

4. The method of claim 1, wherein said etching step includes a wet etch processing using HF, H₂SO₄, H₃PO₄ or HNO₃.

5. The method of claim 1, further comprising the step of processing said first high-K dielectric layer to lower said etch rate of said first high-K dielectric layer.

6. The method of claim 5, wherein said processing step includes the step of annealing said first high-K dielectric layer before forming said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.

7. The method of claim 6, wherein said annealing step occurs in-situ with said first and second dielectric layer forming steps.

8. The method of claim 6, wherein an anneal temperature of said anneal step is at between about 500 and 1000°

C.

9. The method of claim 8, wherein said annealing occurs in a nitrogen, ammonia, oxygen, nitric oxide or nitrous oxide ambience.

10. A method of manufacturing an integrated circuit device, comprising the following steps:

forming a first high-K dielectric layer in a first area defined for a first gate structure of a first device and in a second area defined for a second gate structure of a second device;

processing said first high-K dielectric layer to lower an etch rate to an etchant of said first high-K dielectric layer;

forming a second high-K dielectric layer in said first and second areas over said first high-K dielectric layer, said first high-K dielectric layer having a lower etch rate to said etchant relative to said second high-K dielectric layer;

etching said second high-K dielectric layer from said second area to said first high-K dielectric layer.

11. The method of claim 10, further comprising the step of forming an interfacial layer between said substrate and said first high-K layer in said first and second areas.

12. The method of claim 10, wherein said first and second high-K dielectric layers are formed from different materials.

13. The method of claim 10, wherein said processing step includes the step of annealing said first high-K dielectric layer before forming said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.

14. The method of claim 13, wherein said first and second high-K dielectric layer comprise a first high-K dielectric material.

15. The method of claim 13, wherein an anneal temperature of said anneal step is at between about 500 and 1000°

C., and said annealing occurs in situ with said forming steps in a nitrogen, ammonia, oxygen, nitric oxide or nitrous oxide ambience.

16. The method of claim 10, wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.

17. The method of claim 16, wherein said etching step includes a wet etch processing using HF, H₂SO₄, H₃PO₄ or HNO₃.

18. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

forming a first dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;

forming a second dielectric layer in said first and second areas, said first dielectric layer having a lower etch rate to an etchant relative to said second dielectric layer;

etching said second dielectric layer from said second area to said first dielectric layer wit said etchant; and

forming a gate conductive layer in said first and second areas over said second dielectric layer and first dielectric layer, respectively,

wherein said first dielectric layer is a high-K dielectric layer and said second dielectric layer is a non high-K dielectric layer, and

wherein said first and second areas comprise channel areas having the same conductivity.

19. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;

forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer;

forming an interfacial layer between said substrate and said first high-K dielectric layer in said first and second areas;

etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and

forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.

20. The method of claim 19,

wherein said first high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said second gate structure, and

wherein said second high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said first gate structure minus said target thickness for said gate dielectric for said second gate structure.

21. The method of claim 19, wherein said first and second high-K dielectric layers are formed from different materials.

22. The method of claim 19, further comprising the step of annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer alter said etching step.

23. The method of claim 19, wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.

24. The method of claim 19, wherein said etching step includes a wet etch processing using HF, H₂SO₄, H₃PO₄ or HNO₃.

25. The method of claim 19, further comprising the step of annealing said first high-K dielectric layer before forming said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.

26. The method of claim 25, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.

27. The method of claim 25, wherein said annealing step occurs in-situ with said first and second high-K dielectric forming steps.

28. The method of claim 25, wherein an anneal temperature of said anneal step is at between about 500 and 1000°

C.

29. The method of claim 28, wherein said annealing occurs in a nitrogen, ammonia, oxygen, nitric oxide or nitrous oxide ambience.

30. A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;

forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer;

etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant;

annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer after said etching step; and

forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.

31. The method of claim 30,

wherein said first high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said second gate structure, and

wherein said second high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said first gate structure minus said target thickness for said gate dielectric for said second gate structure.

32. The method of claim 30, wherein said etching step includes a wet etch processing using HF, H₂SO₄, H₃PO₄ or HNO₃.

33. The method of claim 30, wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.

34. The method of claim 30, further comprising the step of annealing said first high-K dielectric layer before fanning said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.

35. The method of claim 34, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.