CMOS imager for pointing and tracking applications

• US 7,030,356 B2
• Filed: 12/16/2002
• Issued: 04/18/2006
• Est. Priority Date: 12/14/2001
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yang, Guang, Pain, Bedabrata, Sun, Chao, Heynssens, Julie B.
• Primary Examiner(s): Allen, Stephone B.
• Application Number:
  US10/321,300
• Publication Number:
  US 20030183850A1
• Time in Patent Office: 1,219 Days
• Field of Search: 250/208.1, 348/241, 348/294, 348301-310
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals

Abstract

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Claims

1. An integrated semiconductor device comprising:

an active pixel sensor array;

a diagonal switch array coupled with the active pixel sensor array;

a memory array coupled with the diagonal switch array;

a readout block coupled with the memory array; and

a controller configurable to operate the diagonal switch array, the memory array, and the readout block in a tracking mode to read out two or more windows in the active pixel sensor array.

2. The device of claim 1, the controller being further configurable to operate the diagonal switch array, the memory array, and the readout block in a second mode.

3. The device of claim 2, wherein the tracking mode employs a sample-first-read-later readout scheme, and the second mode comprises a full-frame mode that employs a row-at-a-time readout scheme.

4. The device of claim 2, wherein the controller operates the diagonal switch array, the memory array, and the readout block in the tracking mode to effect correlated double sampling of pixels in the active pixel sensor array.

5. The device of claim 4, wherein the pixels in the active pixel sensor array comprise photodiode pixels.

6. The device of claim 5, wherein the memory array comprises a memory array configured to handle two separate windows at a time, with a total of eight windows per frame.

7. The device of claim 6, wherein a window size comprises a programmable window size.

8. The device of claim 5, wherein the diagonal switch array comprises one or more low-power, programmable diagonal switch arrays configurable to route a pixel common to two windows into separate memory elements.

9. The device of claim 5, wherein the active pixel sensor array comprises a symmetric pixel array.

10. The device of claim 5, further comprising an A/D converter.

11. The device of claim 10, wherein the readout block comprises a capacitative transimpedance amplifier.

12. A method comprising:

sampling multiple rows and multiple columns of an active pixel sensor array into an on-chip analog memory array; and

reading out the multiple rows and multiple columns sampled in the on-chip memory array to provide image data with reduced motion artifact;

wherein said sampling multiple rows and multiple columns comprises sampling multiple arbitrarily placed windows in the active pixel sensor array; and

wherein said sampling multiple arbitrarily placed windows comprises sampling in a first of two or more operation modes, the first operation mode comprising a tracking mode having low power operation based at least in part on drawing current for sampling only on pixels from the active pixel sensor array that fall in the multiple arbitrarily placed windows.

13. The method of claim 12, wherein sampling multiple rows and multiple columns comprises sampling reset and signal levels of photodiode pixels in the active pixel sensor array.

14. The method of claim 13, wherein reading out the multiple rows and multiple columns comprises performing correlated double sampling using the sampled reset and signal levels.

15. The method of claim 12, wherein sampling multiple arbitrarily placed window further comprises sampling reset and signal levels of photodiode pixels such that correlated signals fall on adjacent capacitor blocks in the on-chip analog memory array, the adjacent capacitor blocks being laid out in a common centroid fashion to reduce fixed pattern noise.

16. The method of claim 15, wherein reading out the multiple rows and multiple columns comprises performing correlated double sampling for the arbitrarily placed windows.

17. The method of claim 15, wherein reading out the multiple rows and multiple columns comprises performing correlated quadruple sampling for the arbitrarily placed windows.

18. An imaging system comprising:

an active pixel sensor array;

a memory array coupled with the active pixel sensor array;

a readout block coupled with the memory array; and

a controller configurable to operate the memory array, the readout block in multiple modes, including a first mode employing a sample-first-read-later readout scheme, and

a diagonal switch array coupled between the active pixel sensor array and the memory array.

19. The imaging system of claim 18, wherein the first mode allows readout of multiple windows in the active pixel sensor array using a single command.

20. The imaging system of claim 19, wherein the controller comprises a memory controller, a row controller, and a column controller.

21. The imaging system of claim 19, wherein the multiple windows comprise two or more arbitrarily placed windows.

22. The imaging system of claim 19, wherein the multiple windows have a programmable size.

23. The imaging system of claim 19, wherein a second mode of the multiple modes allows readout of up to two windows in the active pixel sensor array using another single command.

24. The imaging system of claim 19, wherein the diagonal switch array comprises a low-power diagonal switch array when used with the first mode.

25. The imaging system of claim 18, the controller being further configurable to operate the memory array, and the readout block in the first mode to effect correlated double sampling of pixels in the active pixel sensor array.

26. The imaging system of claim 25, the controller being further configurable to operate the memory array, and the readout block in the first mode to effect correlated quadruple sampling of pixels in the active pixel sensor array.

27. The imaging system of claim 18, wherein the memory array comprises adjacent capacitors in a common centroid layout, and the controller arranges correlated values on the adjacent capacitors to reduce fixed pattern noise when performing correlated sampling of signal levels and reset levels.

28. An imaging system comprising:

an active pixel sensor array;

a memory array coupled with the active pixel sensor array;

a readout block coupled with the memory array; and

a controller configurable to operate the memory array, and the readout block in multiple modes, including a first mode employing a sample-first-read-later readout scheme, and

wherein the memory array comprises adjacent capacitors in a common centroid layout, and the controller arranges correlated values on the adjacent capacitors to reduce fixed pattern noise when performing correlated sampling of signal levels and reset levels, and

wherein the active pixel sensor array comprises a photodiode array, each photodiode having a common photo-conversion and sense node.

29. The imaging system of claim 28, wherein the active pixel sensor array further comprises a symmetric pixel array.

30. The imaging system of claim 29, further comprising an A/D converter.

31. The imaging system of claim 30, wherein the readout block comprises a capacitative transimpedance amplifier.

32. The imaging system of claim 30, further comprising a star-tracker system in communication with an active pixel sensor system comprising the active pixel sensor array, a diagonal switch array, the memory array, the readout block, the A/D converter, and the controller.

33. An integrated semiconductor device comprising:

an active pixel sensor array;

a memory array coupled with the active pixel sensor array;

a readout block coupled with the memory array; and

a controller configurable to operate the memory array and the readout block to perform four-point correlated double sampling, wherein the controller operates the memory array and the readout block to perform four-point correlated double sampling by placing correlated signals on adjacent capacitor blocks that have been laid out in the memory array in a common centroid fashion.

34. The device of claim 33, the controller being further configurable to operate the memory array and the readout block to perform two-point correlated double sampling.

35. An integrated semiconductor device comprising:

an active pixel sensor array;

a memory array coupled with the active pixel sensor array;

a readout block coupled with the memory array; and

a controller configurable to operate the memory array and the readout block to perform four-point correlated double sampling,

wherein the controller operates the memory array and the readout block to perform four-point correlated double sampling by placing differential signals on capacitor blocks in the memory array such that only one subtraction is used for each four samples.

36. An integrated semiconductor device comprising:

an active pixel sensor array;

a memory array coupled with the active pixel sensor array;

a readout block coupled with the memory array;

a controller configurable to operate the memory array and the readout block to perform four-point correlated double sampling, and

a diagonal switch array coupled between the active pixel sensor array and the memory array, wherein the controller is further configurable to operate the diagonal switch array, the memory array, and the readout block in a tracking mode to read out multiple windows per frame in the active pixel sensor array.