Minimally-patterned semiconductor devices for display applications

• US 7,030,412 B1
• Filed: 05/05/2000
• Issued: 04/18/2006
• Est. Priority Date: 05/05/1999
• Status: Expired due to Fees

• Current Assignee: E Ink Corporation (E Ink Holdings Incorporated)
• Original Assignee: E Ink Corporation (E Ink Holdings Incorporated)
• Inventors: Chen, Yu, Kazlas, Peter T., Amundson, Karl R., Drzaic, Paul S., Duthaler, Gregg M.
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US09/565,413
• Time in Patent Office: 2,174 Days
• Field of Search: 438149-166, 438/FOR.201, 438/FOR.184, 257/347, 257/348, 257/349, 257/350, 257/52, 257/55, 257/57, 257/66, 257/59, 257/60, 257/67, 257/69, 257/70, 257/77, 257/E29.151, 257/E51.005, 349 42- 45, 345/90, 345/92
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657

Abstract

A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The semiconductor layer is preferably unpatterned. In various display applications, the geometry of the transistors is selected to provide acceptable leakage currents. In a preferred embodiment, the transistor array is employed in an encapsulated electrophoretic display.

Claims

1. A thin-film transistor array comprising at least first, second and third transistors, each of the transistors comprising:

a source electrode;

a drain electrode spaced from the source electrode;

a semiconductor layer in electrical communication with both the source and drain electrodes; and

a gate electrode disposed adjacent to the semiconductor layer for varying the resistance of the semiconductor layer between the source and drain electrodes by varying a potential of the gate electrode,

the transistor array further comprising;

a first data line in communication with one of the source and drain electrodes of each of the first and second transistors;

a second data line in communication with a corresponding one of the source and drain electrodes of the third transistor;

a first select line in communication with the gate electrodes of the first and third transistors; and

a second select line in communication with the gate electrode of the second transistor,

wherein the semiconductor layer extends continuously among the first, second and third transistors.

2. The thin-film transistor array of claim 1 wherein the semiconductor layer is unpatterned.

3. The thin-film transistor array of claim 2 further including a dielectric layer adjacent to the semiconductor layer, wherein the dielectric layer is unpatterned.

4. The thin-film transistor array of claim 1 wherein the first transistor is a bottom gate transistor.

5. The thin-film transistor array of claim 1 wherein the first transistor is a top gate transistor.

6. The thin-film transistor array of claim 1 wherein the first transistor further includes a first pixel electrode of an electronic display, the first pixel electrode in communication with the drain electrode of the first transistor, the second transistor further includes a second pixel electrode of the electronic display, the second pixel electrode in communication with the drain electrode of the second transistor, the third transistor further includes a third pixel electrode of the electronic display, the third pixel electrode in communication with the drain electrode of the third transistor, and the source electrode of the first transistor is in communication with the first data line, the source electrode of the second transistor is in communication with the second data line and the source electrode of the third transistor is in communication with the second data line.

7. The thin-film transistor array of claim 6 wherein a distance between the first pixel electrode and the first data line is selected to provide an acceptable leakage between the first pixel electrode and the first data line.

8. The thin-film transistor array of claim 6 wherein a distance between the first transistor and the second transistor is selected to provide an acceptable leakage between the first data line and the second data line.

9. The thin-film transistor array of claim 8 wherein at least one of the first data line, the second data line, the first transistor and the first pixel electrode have a geometry selected to provide an acceptable leakage between the first data line and the second data line.

10. The thin-film transistor array of claim 1 wherein the semiconductor layer comprises an organic semiconductor material.

11. The thin-film transistor array of claim 1 wherein the semiconductor layer comprises silicon.

12. The thin-film transistor array of claim 11 wherein the semiconductor layer comprises amorphous silicon.

13. The thin-film transistor array of claim 11 wherein the semiconductor layer comprises amorphous silicon with a p-type dopant.

14. The thin-film transistor array of claim 6 wherein the first transistor further comprises a patterned n-doped silicon layer provided between the semiconductor layer and at least one of the source electrode of the first transistor and the drain electrode of the first transistor.

15. The thin-film transistor array of claim 1 wherein the first transistor further comprises a passivation layer provided adjacent to the semiconductor layer.