Gate dielectric antifuse circuits and methods for operating same

• US 7,030,458 B2
• Filed: 10/06/2003
• Issued: 04/18/2006
• Est. Priority Date: 08/31/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US10/680,481
• Publication Number:
  US 20040065941A1
• Time in Patent Office: 925 Days
• Field of Search: 257/528, 257/529, 257/530
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a first terminal coupled to the common bus line is selected to be programmed by a control transistor in a program driver circuit coupled to a second terminal of the antifuse. The program driver circuit has a high-voltage transistor with a diode coupled to its gate to bear a portion of the elevated voltage after the antifuse has been programmed. The program driver circuit also has an impedance transistor between the high-voltage transistor and the control transistor to reduce leakage current and the possibility of a snap-back condition in the control transistor. A read circuit includes a transistor coupled between a read voltage source and the second terminal to read the antifuse in an active mode. The common bus line may be coupled to a reference voltage through a common bus line driver circuit in the active mode to pass current to or from the read circuit. The common bus line driver circuit has a control transistor and a high-voltage transistor with a diode coupled to its gate to bear the elevated voltage on the common bus line during the programming mode. The read circuit may have a latch circuit to latch a state of the antifuse in a sleep mode. A floating well driver logic circuit raises the voltage potential of wells and gate terminals of p-channel transistors in the read circuit during the programming mode to reduce current flow from the common bus line.

Claims

1. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a reference voltage and a second terminal; and

a read circuit to read the antifuse, the read circuit comprising;

a read transistor coupled between a read voltage and the antifuse to couple the read voltage to the antifuse to read the antifuse during an active mode; and

a latch circuit to latch a state of the antifuse during a sleep mode.

2. The antifuse circuit of claim 1 wherein:

the antifuse comprises a gate dielectric between the first terminal and the second terminal, the first terminal being coupled to a ground voltage reference; and

the read transistor comprises a p-channel transistor having a source terminal coupled to the read voltage, a gate terminal coupled to a bias voltage, and a drain terminal coupled to the second terminal of the antifuse;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors.

4. The antifuse circuit of claim 1 wherein:

the read transistor comprises a p-channel read transistor having a source terminal coupled to the read voltage and a gate terminal coupled to a bias voltage;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

further comprising a p-channel transistor coupled between the read transistor and the second terminal of the antifuse that is switched on when the antifuse is being read.

5. The antifuse circuit of claim 1, further comprising:

an external pin coupled to a common bus line to couple an elevated voltage to the first terminal of the antifuse to program the antifuse during a programming mode;

a program driver circuit coupled to the second terminal of the antifuse to select the antifuse to be programmed during the programming mode, the program driver circuit comprising a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage reference;

a floating well driver logic circuit coupled to a gate terminal and a well of a p-channel transistor in the read circuit or the latch circuit to raise a voltage of the gate terminal and the well during the programming mode to substantially prevent current in the p-channel transistor; and

wherein the read circuit further comprises a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit.

6. The antifuse circuit of claim 1 wherein:

the antifuse comprises a gate dielectric between the first terminal and the second terminal, the first terminal being coupled to a ground voltage reference;

the read transistor comprises an n-channel transistor having a drain terminal coupled to the read voltage, a gate terminal coupled to a bias voltage, and a source terminal coupled to the second terminal of the antifuse;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of n-channel latch circuit transistors and an output coupled to gate terminals of the n-channel latch circuit transistors; and

further comprising an n-channel transistor coupled between the read transistor and the second terminal of the antifuse that is switched on when the antifuse is being read.

7. The antifuse circuit of claim 1 wherein the antifuse comprises a gate dielectric between the first terminal comprising n-type material and the second terminal comprising p-type material, the first terminal being coupled to a ground voltage reference and the second terminal being coupled to the read circuit.

8. The antifuse circuit of claim 1 wherein:

the antifuse comprises a gate dielectric between the first terminal comprising n-type material and the second terminal comprising n-type material, the first terminal being coupled to a voltage source;

the read transistor comprises a long-L n-channel transistor having a source terminal coupled to a ground voltage reference, a gate terminal coupled to a bias voltage, and a drain terminal coupled to the second terminal of the antifuse; and

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors.

3. A method of operating an antifuse circuit comprising:

coupling a reference voltage to a first terminal of an antifuse;

coupling a read voltage to a second terminal of the antifuse through a read transistor;

detecting a voltage of the second terminal of the antifuse to read the antifuse during an active mode; and

latching the voltage of the second terminal of the antifuse during a sleep mode.

9. The method of claim 3 wherein:

coupling a read voltage further comprises coupling the read voltage to the second terminal of the antifuse through a p-channel read transistor switched on by a bias voltage during the active mode;

detecting a voltage further comprises detecting the voltage of the second terminal of the antifuse with an input of an inverter during the active mode;

latching the voltage further comprises latching the voltage of the second terminal of the antifuse with a latch circuit comprising the inverter coupled to a plurality of latch transistors; and

further comprising switching on a p-channel transistor coupled between the read transistor and the second terminal of the antifuse during the active mode.

10. The method of claim 3, further comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and the first terminal of the antifuse to program the antifuse with the elevated voltage during a programming mode;

switching on a control transistor coupled in series with a high-voltage transistor between the second terminal of the antifuse and a ground voltage reference to select the antifuse to be programmed during the programming mode, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse; and

switching off transistors in a read circuit coupled to the antifuse during the programming mode with a floating well driver logic circuit coupled to the read circuit by raising a voltage of a gate terminal and a well of a p-channel transistor to substantially prevent current in the p-channel transistor.

11. The method of claim 3 wherein:

coupling a reference voltage comprises coupling a ground voltage reference to a first terminal of an antifuse;

coupling a read voltage comprises coupling a read voltage to a second terminal of the antifuse through an n-channel read transistor switched on by a bias voltage;

detecting a voltage comprises detecting a voltage of the second terminal of the antifuse with an input of an inverter during an active mode; and

latching the voltage comprises latching the voltage of the second terminal of the antifuse with a latch circuit including the inverter coupled to a plurality of n-channel latch transistors during a sleep mode.

12. The method of claim 3 wherein:

coupling a reference voltage to a first terminal of an antifuse further comprises coupling the reference voltage to the first terminal comprising n-type material; and

coupling a read voltage to a second terminal of the antifuse further comprises coupling the read voltage to the second terminal of the antifuse comprising p-type material, the second terminal of the antifuse being separated from the first terminal of the antifuse by a gate dielectric.

13. The method of claim 3 wherein:

coupling a reference voltage comprises coupling a voltage source to a first terminal of an antifuse, the first terminal comprising n-type material;

coupling a read voltage comprises coupling a ground voltage reference to a second terminal of the antifuse through an n-channel read transistor switched on by a bias voltage, the second terminal comprising n-type material;

detecting a voltage comprises detecting a voltage of the second terminal of the antifuse with an input of an inverter; and

latching the voltage comprises latching the voltage of the second terminal of the antifuse with a latch circuit including the inverter coupled to a plurality of latch circuit transistors.

14. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a reference voltage, the reference voltage and a second terminal; and

a read circuit to read the antifuse, the read circuit comprising;

a transistor coupled between a read voltage and the antifuse to couple the read voltage to the antifuse to read the antifuse; and

an inverter having an input coupled to the second terminal of the antifuse.

15. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a reference voltage and a second terminal; and

a read circuit to read the antifuse, the read circuit comprising a transistor coupled between a read voltage and the antifuse to couple the read voltage to the antifuse to read the antifuse, wherein;

the antifuse comprises a gate dielectric between the first terminal and the second terminal, the first terminal being coupled to a ground voltage reference;

the transistor comprises a p-channel transistor having a source terminal coupled to the read voltage and a gate terminal coupled to a bias voltage; and

the read circuit further comprises an inverter having an input coupled to the second terminal of the antifuse.

16. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a reference voltage and a second terminal;

a read circuit to read the antifuse, the read circuit comprising a transistor coupled between a read voltage and the antifuse to couple the read voltage to the antifuse to read the antifuse;

an external pin coupled to a common bus line to couple an elevated voltage to the first terminal of the antifuse to program the antifuse during a programming mode;

a program driver circuit coupled to the second terminal of the antifuse to select the antifuse to be programmed during the programming mode, the program driver circuit comprising a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage reference;

a floating well driver logic circuit coupled to a well of a p-channel transistor in the read circuit to raise a voltage of the well during the programming mode to substantially prevent current in the p-channel transistor; and

wherein the read circuit further comprises a plurality of p-channel transistors, one of the p-channel transistors being coupled between the second terminal of the antifuse and the floating well driver logic circuit to couple a rising voltage on the second terminal of the antifuse to the floating well driver logic circuit.

17. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a reference voltage and a second terminal; and

a read circuit to read the antifuse, the read circuit comprising a transistor coupled between a read voltage and the antifuse to couple the read voltage to the antifuse to read the antifuse, wherein the antifuse comprises a gate dielectric between the first terminal comprising n-type material and the second terminal comprising p-type material, the first terminal being coupled to a ground voltage reference and the second terminal being coupled to the read circuit.

18. A method of operating an antifuse circuit comprising:

coupling a reference voltage to a first terminal of an antifuse;

coupling a read voltage to a second terminal of the antifuse through a transistor; and

detecting a voltage of the second terminal of the antifuse to read the antifuse the second terminal coupled to an input of an inverter.

19. The method of claim 18 wherein:

coupling a reference voltage comprises coupling a ground voltage reference to a first terminal of an antifuse;

coupling a read voltage comprises coupling a read voltage to a second terminal of the antifuse through a p-channel transistor switched on by a bias voltage; and

detecting a voltage comprises detecting a voltage of the second terminal of the antifuse with an input of the inverter.

20. The method of claim 18, further comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and the first terminal of the antifuse to program the antifuse with the elevated voltage during a programming mode;

switching on a control transistor coupled in series with a high-voltage transistor between the second terminal of the antifuse and a ground voltage reference to select the antifuse to be programmed during the programming mode, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse; and

switching off a p-channel transistor in a read circuit coupled to the antifuse during the programming mode with a floating well driver logic circuit coupled to the read circuit by raising a voltage of a well of the p-channel transistor to substantially prevent current in the p-channel transistor.

21. The method of claim 18 wherein:

coupling a reference voltage to a first terminal of an antifuse further comprises coupling the reference voltage to the first terminal comprising n-type material; and

coupling a read voltage to a second terminal of the antifuse further comprises coupling the read voltage to the second terminal of the antifuse comprising p-type material, the second terminal of the antifuse being separated from the first terminal of the antifuse by a gate dielectric.

22. An antifuse circuit comprising:

an antifuse having a first terminal coupled to a reference voltage and a second terminal;

a read circuit to read the antifuse, the read circuit comprising;

a read transistor coupled between a read voltage and the antifuse to couple the read voltage to the antifuse to read the antifuse during an active mode; and

a latch circuit to latch a state of the antifuse during a sleep mode; and

a pass-gate device coupled between the antifuse and the read circuit.

23. The antifuse circuit of claim 22 wherein:

the antifuse comprises a gate dielectric between the first terminal and the second terminal, the first terminal being coupled to a ground voltage reference;

the read transistor comprises a p-channel transistor having a source terminal coupled to the read voltage, a gate terminal coupled to a bias voltage, and a drain terminal coupled to the second terminal of the antifuse;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

further comprising a p-channel transistor coupled between the read transistor and the pass gate device that is switched on when the antifuse is being read.

24. The antifuse circuit of claim 22 wherein:

the antifuse comprises a gate dielectric between the first terminal and the second terminal, the first terminal being coupled to a ground voltage reference;

the read transistor comprises an n-channel transistor having a drain terminal coupled to the read voltage, a gate terminal coupled to a bias voltage, and a source terminal coupled to the second terminal of the antifuse;

the latch circuit comprises an inverter having an input coupled to the second terminal of the antifuse and to a plurality of latch circuit transistors and an output coupled to gate terminals of the latch circuit transistors; and

further comprising an n-channel transistor coupled between the read transistor and the pass gate device that is switched on when the antifuse is being read.

25. The antifuse circuit of claim 22 wherein the antifuse comprises a gate dielectric between the first terminal comprising n-type material and the second terminal comprising p-type material, the first terminal being coupled to a ground voltage reference and the second terminal being coupled to the read circuit.

26. The antifuse circuit of claim 22 wherein the pass-gate device comprises an n-channel pass-gate transistor comprising a gate coupled to the read voltage.

27. The antifuse circuit of claim 22 wherein the pass-gate device comprises an n-channel pass-gate transistor comprising a gate coupled to a voltage different from the read voltage.

28. The antifuse circuit of claim 22, further comprising:

an external pin coupled to a common bus line to couple an elevated voltage to the first terminal of the antifuse to program the antifuse during a programming mode; and

a program driver circuit coupled to the second terminal of the antifuse to select the antifuse to be programmed during the programming mode, the program driver circuit comprising a high-voltage transistor and a control transistor coupled in series between the second terminal of the antifuse and a ground voltage reference.

29. A method of operating an antifuse circuit comprising:

coupling a reference voltage to a first terminal of an antifuse;

coupling a read voltage to a second terminal of the antifuse through a read transistor and a pass-gate device;

detecting a voltage of the second terminal of the antifuse to read the antifuse during an active mode; and

latching the voltage of the second terminal of the antifuse during a sleep mode.

30. The method of claim 29 wherein:

coupling a reference voltage comprises coupling a ground voltage reference to a first terminal of an antifuse;

coupling a read voltage comprises coupling a read voltage to a second terminal of the antifuse through a p-channel read transistor switched on by a bias voltage and a pass-gate device;

detecting a voltage comprises detecting a voltage of the second terminal of the antifuse with an input of an inverter during an active mode;

latching the voltage comprises latching the voltage of the second terminal of the antifuse with a latch circuit including the inverter coupled to a plurality of latch transistors during a sleep mode; and

further comprising switching on a p-channel transistor coupled between the read transistor and the pass gate device during the active mode.

31. The method of claim 29 wherein:

coupling a reference voltage comprises coupling a ground voltage reference to a first terminal of an antifuse;

coupling a read voltage comprises coupling a read voltage to a second terminal of the antifuse through an n-channel read transistor switched on by a bias voltage and a pass-gate device;

detecting a voltage comprises detecting a voltage of the second terminal of the antifuse with an input of an inverter during an active mode;

latching the voltage comprises latching the voltage of the second terminal of the antifuse with a latch circuit including the inverter coupled to a plurality of latch transistors during a sleep mode; and

further comprising switching on an n-channel transistor coupled between the read transistor and the pass gate device during the active mode.

32. The method of claim 29, further comprising controlling current flow between the antifuse and the read transistor with the pass-gate device, the pass-gate device comprising an n-channel pass-gate transistor comprising a gate coupled to the read voltage.

33. The method of claim 29, further comprising controlling current flow between the antifuse and the read transistor with the pass-gate device, the pass-gate device comprising an n-channel pass-gate transistor comprising a gate coupled to a voltage different from the read voltage.

34. The method of claim 29 wherein:

coupling a reference voltage to a first terminal of an antifuse further comprises coupling the reference voltage to the first terminal comprising n-type material; and

coupling a read voltage to a second terminal of the antifuse further comprises coupling the read voltage to the second terminal of the antifuse comprising p-type material, the second terminal of the antifuse being separated from the first terminal of the antifuse by a gate dielectric.

35. The method of claim 29, further comprising:

coupling an elevated voltage to an external pin coupled to a common bus line and the first terminal of the antifuse to program the antifuse with the elevated voltage during a programming mode; and

switching on a control transistor coupled in series with a high-voltage transistor between the second terminal of the antifuse and a ground voltage reference to select the antifuse to be programmed during the programming mode, the antifuse comprising a gate dielectric between the first terminal and the second terminal of the antifuse.

36. An integrated circuit comprising:

an antifuse having a first terminal coupled to a common bus line;

a program driver circuit coupled to a second terminal of the antifuse to select the antifuse to be programmed during a programming mode;

means for reading the antifuse during an active mode; and

a latch circuit coupled to the second terminal of the antifuse to latch a state of the antifuse during a sleep mode.