Method and apparatus for generating narrow pulse width monocycles

• US 7,030,663 B2
• Filed: 09/04/2002
• Issued: 04/18/2006
• Est. Priority Date: 09/04/2001
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor (NXP Semiconductors NV)
• Inventors: McCorkle, John W., Huynh, Phuong T., Ochoa, Agustin
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US10/233,534
• Publication Number:
  US 20030076136A1
• Time in Patent Office: 1,322 Days
• Field of Search: 327108-112, 327/170, 327172-175, 327/291, 327/423, 327/436, 327/437, 327/589
• US Class Current: 327/108
• CPC Class Codes: G01S 7/282 Transmitters
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03K 7/04 Position modulation, i.e. PPM
• CPC Class Codes: H04B 1/7174 Pulse generation in general H04L25/03834

Abstract

A monocycle forming network may include a monocycle generator, up and down pulse generators, data modulators and clock generation circuits. The network may generate monocycle pulses having very narrow pulse widths, approximately 80 picoseconds peak to peak. The monocycles may be modulated to carry data in ultra-wideband communication systems.

Claims

1. A monocycle generator, comprising:

a pair of transistors, a first transistor coupled to a first voltage source, a second transistor coupled to a second voltage source, both the first and second transistors coupled to a common output terminal,

means for maintaining the output terminal at a voltage intermediate between the first and second voltages when the first and second transistors are non-conductive,

a third transistor coupling the means to the first voltage source,

a fourth transistor coupling the means to the second voltage source, and

a second pair of transistors, one coupled to the first voltage source, another coupled to the second voltage source, both coupled to a second output terminal,

wherein the means comprises a third pair of transistors bridging between the first and second output terminals and a reference potential coupled to a node between the third pair of transistors.

2. The monocycle generator of claim 1, wherein the means comprises a voltage divider.

3. The monocycle generator of claim 1, wherein the means comprises a voltage regulator.

4. The monocycle generator of claim 1, wherein inputs of the first and fourth transistors are coupled to a common signal source and the first and fourth transistors are of different device types.

5. The monocycle generator of claim 1, wherein inputs of the second and third transistors are coupled to a common signal source and the second and third transistors are of different device types.

6. The monocycle generator of claim 1, further comprising a down pulse generator coupled to an input of the first transistor, the down pulse generator comprising:

a pair of pull up transistors each bridging an input of the first transistor to the first voltage source,

an input of the first pull up transistor coupled to a first clock source,

an input of the second pull up transistor coupled to a second clock source that is delayed and inverted with respect to first clock source,

a first pull down transistor bridging the input of the first transistor to the second voltage source,

a second pull down transistor bridging an input of the first pull down transistor to the second voltage source, an input of the second pull down transistor coupled to a third clock source that is delayed with respect to the first clock source,

a gate having an input coupled to the first clock source, an output coupled to the input of the first pull down transistor and a control input coupled to the second clock source.

7. The monocycle generator of claim 1, further comprising an up pulse generator coupled to an input of the second transistor, the up pulse generator comprising:

a pair of pull down transistors each bridging the input of the second transistor to the second voltage source,

the first pull down transistor coupled to a first clock source,

the second pull down transistor coupled to a second clock source that is delayed and inverted with respect to the first clock source,

a first pull up transistor bridging the input of the second transistor to the second voltage source,

a second pull up transistor bridging an input of the first pull up transistor to the second voltage source, an input of the second pull up transistor coupled to a third clock source that is delayed with respect to the first clock source,

a gate having an input coupled to the first clock source, an output coupled to the input of the first pull up transistor and a control input coupled to the third clock source.

8. The monocycle generator of claim 1, wherein the first and second transistors are conductive in response to an active portion of an up pulse signal.

9. The monocycle generator of claim 1, wherein the first voltage source comprises:

a delay block having an input for a clock signal,

a phase detector having an input for the clock signal and a second input coupled to the delay block, and

a charge pump coupled to the phase detector having an output coupled to the first and third transistors and to the delay block.

10. A monocycle generator, comprising:

a pair of pull up transistors, each coupled to respective ones of first and second output terminals and to a first voltage source,

a pair of pull down transistors, each coupled to respective ones of the first and second output terminals and to a second voltage source,

a pair of transistors bridging between the first and second output terminals,

a reference potential coupled to a node between the two bridging transistors,

wherein the pair of transistors bridging between the first and second output terminals are made conductive when all of the pull up and pull down transistors are non-conductive, and are made non-conductive when any of the pull up and pull down transistors are conductive.

11. The monocycle generator of claim 10, wherein:

the pull up transistor coupled to the first output terminal and the pull down transistor coupled to the second output terminal are conductive in response to a first set of activation pulses,

the pull up transistor coupled to the second output terminal and the pull down transistor coupled to the first output terminal are conductive in response to a second set of activation pulses, and

timing of the respective sets of activation pulse is modulated in response to an information signal.