Frequency boosting circuit for high swing cascode biasing circuits

• US 7,030,685 B1
• Filed: 06/30/2005
• Issued: 04/18/2006
• Est. Priority Date: 02/27/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Aram, Farbod
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US11/170,926
• Time in Patent Office: 292 Days
• Field of Search: 323/312, 323/313, 323/314, 323/315, 323/316, 327/530, 327/534, 327/535, 327/537, 327/538, 327/540, 327/541, 327/542, 327/543, 327/551, 327/552, 327/558, 327/559, 330/292, 330/294, 330/296
• US Class Current: 327/538
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A high swing cascode biasing circuit includes a frequency boosting circuit that improves the frequency response of the high swing cascode biasing circuit. The high swing cascode biasing circuit may be implemented in Ahuja compensation circuits or other circuits.

Claims

1. A high swing cascode biasing circuit, comprising:

a current biasing circuit that generates a cascode bias and a main bias;

a frequency boosting circuit that receives said cascode bias and said main bias and that generates a second bias; and

a current mirror circuit that receives said main bias and said second bias and that generates feedback for said frequency boosting circuit.

2. The high swing cascode biasing circuit of claim 1 wherein said current mirror includes a first transistor and wherein said feedback increases a transconductance of said first transistor.

3. The high swing cascode biasing circuit of claim 1 wherein said frequency boosting circuit increases a bandwidth of said high swing cascode biasing circuit.

4. An Ahuja compensation circuit comprising the high swing cascode biasing circuit of claim 1.

5. A high swing cascode biasing circuit, comprising:

current biasing means for generating a cascode bias and a main bias;

frequency boosting means for receiving said cascode bias and said main bias, for generating a second bias, and for boosting a frequency response of said high swing cascode biasing circuit; and

current mirror means for receiving said main bias and said second bias and for generating feedback for said frequency boosting means.

6. The high swing cascode biasing circuit of claim 5 wherein said current mirror means includes a first transistor and wherein said feedback increases a transconductance of said first transistor.

7. The high swing cascode biasing circuit of claim 5 wherein said frequency boosting means increases a bandwidth of said high swing cascode biasing circuit.

8. An Ahuja compensation circuit comprising the high swing cascode biasing circuit of claim 5.

9. A method of operating a high swing cascode biasing circuit, comprising:

generating a cascode bias and a main bias;

receiving said cascode bias and said main bias and generating a second bias;

boosting a frequency response of said high swing cascode biasing circuit; and

receiving said main bias and said second bias and generating feedback for said boosting.

10. The method of claim 9 wherein said feedback increases a transconductance of a transistor.

11. The high swing cascode biasing circuit of claim 9 wherein said boosting increases bandwidth of said high swing cascode biasing circuit.