System and method for producing a video signal

• US 7,030,886 B2
• Filed: 10/29/2004
• Issued: 04/18/2006
• Est. Priority Date: 08/06/1999
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Ford, Jeff S., Denton, Claude
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): RAHMJOO, MANUCHER
• Application Number:
  US10/977,019
• Publication Number:
  US 20050122310A1
• Time in Patent Office: 536 Days
• Field of Search: 345/591, 345/723, 345/724, 345/725, 345/726, 345/597
• US Class Current: 345/591
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2340/04 Changes in size, position or resolution of an image
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/50 using predictive coding H04N19/61 takes precedence
• CPC Class Codes: H04N 19/587 involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 for processing graphics
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 9/64 : Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/69 : for modifying the colour signals by gamma correction controlling camera response for colour signals H04N23/83

Abstract

A method and apparatus for producing video signals comprises a receiver for receiving a video signal, a video pipeline for post-processing the received video signal, the video pipeline producing a post-processed video signal, and a video output module for converting the post-processed video signal, the video output module producing a formatted video signal. The video output module may further comprise an ancillary data injector, the injector inserting ancillary data into the post-processed video signal. Also, the video output system may further comprise a generator locking device or the video input module may include a generator locking device.

Claims

1. A system for producing video signals, the system being communicatively coupled by electrical communication paths to a video graphics processor, a video signal input system, and a storage medium for storing data in electrical form, the system comprising:

means for receiving a video signal;

means for post-processing the received video signal, the post-processing means producing a post-processed video signal, wherein the post-processing means includes functionality for performing the following functions;

region of interest selection;

frame rate matching;

spatial adaptation;

changing the sample rate of the video signal being post processed;

gamma removal;

gamma insertion;

color space conversion;

changing frames of video data into interleaved fields of video data; and

addressing on a frame by frame basis the video signal being post processed; and

means for converting the post-processed video signal, the converting means producing a formatted video signal wherein;

the converting means includes;

a means for inserting ancillary data into the post-processed video signal; and

a generator locking device; and

the system is configured to receive the received video signal from the storage medium, the video graphics processor, and the video input system.

2. The system according to claim 1, wherein the received video signal is e-VS, wherein e-VS is an RGB encoded video signal, an RGBA encoded video signal, a YUV-Type encoded video signal, or a YUVA-Type encoded video signal.

3. The system according to claim 1, wherein the system is a Peripheral Component Interconnect circuit board.

4. The system according to claim 1, wherein the receiving means and the post-processing means are implemented as an integrated video processing module, and wherein the converting means is detachably coupled to the video processing module.

5. The system according to claim 4, wherein the converting means is a daughterboard module that couples to the video processing module.

6. The system according to claim 1, wherein the converting means includes a processor that is configured to inform the past-processing means of its configuration.

7. A video output system for producing video signals, the video output system being communicatively coupled by electrical communication paths to a video graphics processor, a video signal input system, and a storage medium for storing data in electrical form, the video output system comprising:

an integrated video processing module having;

a receiver for receiving a video signal; and

a video pipeline for post-processing the received video signal, the video pipeline producing a post-processed video signal, wherein the video pipeline includes functionality for performing the following functions;

region of interest selection;

frame rate matching;

spatial adaptation;

changing the sample rate of the video signal being post processed;

gamma removal;

gamma insertion;

color space conversion;

changing frames of video data into interleaved fields of video data; and

addressing on a frame by frame basis the video signal being post processed; and

a video output module for converting the post-processed video signal, the video output module producing a formatted video signal wherein;

the video output module includes;

an ancillary data injector, the injector inserting ancillary data into the post-processed video signal; and

a generator locking device; and

the video output system is configured to receive the received video signal from the storage medium, the video graphics processor, and the video input system.

8. The video output system according to claim 7, wherein the video output module is detachably coupled to the integrated video processing module.

9. The video output system according to claim 8, wherein the video output module is a daughterboard module that couples to the integrated video processing module.

10. The video output system according to claim 7, wherein the received video signal is e-VS, wherein e-VS is an RGB encoded video signal, an RGBA encoded video signal, a YUV-Type encoded video signal, or a YUVA-Type encoded video signal.

11. The video output system according to claim 7, wherein the video output system is a Peripheral Component Interconnect circuit board.

12. A video output system for producing video signals, the video output system being communicatively coupled by electrical communication paths to a video graphics processor, a video signal input system, and a storage medium for storing data in electrical form, the video output system comprising:

a receiver for receiving a video signal; and

a video pipeline for post-processing the received video signal, the video pipeline producing a post-processed video signal, wherein the video pipeline includes functionality for performing the following functions;

region of interest selection;

flame rate matching;

spatial adaptation;

changing the sample rate of the video signal being post processed;

gamma removal;

gamma insertion;

color space conversion;

changing frames of video data into interleaved fields of video data; and

addressing on a frame by frame basis the video signal being post processed; and

a video output module for converting the post-processed video signal, the video output module producing a formatted video signal wherein;

the video output module includes;

an ancillary data injector, the injector inserting ancillary data into the post-processed video signal;

a processor that is configured to inform the integrated video processing module of a configuration of the video output module; and

a generator locking device; and

the video output system is configured to receive the received video signal from the storage medium, the video graphics processor, and the video input system.

13. The video output system according to claim 12, wherein the receiver and the video pipeline are integrated to form an integrated video processing module.

14. The video output system according to claim 13, wherein the video output module is detachably coupled to the integrated video processing module.

15. The video output system according to claim 13, wherein the video output module is a daughterboard module that couples to the integrated video processing module.

16. The video output system according to claim 12, wherein the received video signal is e-VS, wherein e-VS is an RGB encoded video signal, an RGBA encoded video signal, a YUV-Type encoded video signal, or a YUVA-Type encoded video signal.

17. The video output system according to claim 12, wherein the video output system is a Peripheral Component Interconnect circuit board.