Multi-pulse reset write scheme for phase-change memories

• US 7,031,181 B1
• Filed: 11/23/2004
• Issued: 04/18/2006
• Est. Priority Date: 11/23/2004
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Happ, Thomas
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/995,644
• Time in Patent Office: 511 Days
• Field of Search: 365/148, 365/114
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes

Abstract

A memory cell device and method that includes a memory cell, and first and second write pulse signals. The memory cell has phase-change material capable of being set and capable of being reset. The first and second write pulse signals are used for a single reset operation of the memory cell. The first write pulse signal heats and melts a first portion of the phase-change material of the memory cell. The second write pulse signal heats and melts a second portion of the phase-change material of the memory cell.

Claims

1. A method of resetting a memory cell, the method comprising:

providing a first electrical write pulse to phase-change material within the memory cell;

heating a first portion of the phase-change material with the first write pulse until it is melted;

allowing the first portion of the phase-change material to cool below melting temperate;

providing a second write pulse to the phase-change material within the memory cell;

heating a second portion of the phase-change material with the second write pulse until it is melted; and

allowing the second portion of the phase-change material to cool.

2. The method of claim 1 further comprising:

providing a third write pulse to phase-change material within the memory cell;

heating a third portion of the phase-change material with the third write pulse until it is melted; and

allowing the third portion of the phase-change material to cool.

3. The method of claim 2 further comprising:

providing a fourth write pulse to phase-change material within the memory cell;

heating a fourth portion of the phase-change material with the fourth write pulse until it is melted; and

allowing the fourth portion of the phase-change material to cool.

4. The method of claim 1, wherein heating the first portion and allowing it to cool changes the first portion to an amorphous state having a higher resistivity than remaining portions of the phase-change material.

5. The method of claim 4, wherein upon providing the second write pulse to the phase-change material, the higher resistivity of the first portion causes the heating of the second portion rather than the first portion.

6. The method of claim 1, wherein providing the first write pulse comprises providing one of the group comprising a current pulse and a voltage pulse.

7. The method of claim 1, wherein heating times of the first and second portions are in the range of zero to 5 nanoseconds and cooling times zero to 2 nanoseconds.

8. The method of claim 7, wherein the reset operation takes less than 35 nanoseconds.

9. The method of claim 1, wherein the first write pulse is directed through the phase-change material thereby heating up the material.

10. A memory cell device comprising:

a memory cell having phase-change material capable of being set and capable of being reset;

write pulse means for generating at least first and second write pulse signals for a single reset operation of the memory cell, wherein the first write pulse signal heats and melts a first portion of the phase-change material of the memory cell, and wherein the second write pulse signal heats and melts a second portion of the phase-change material of the memory cell.

11. The memory cell device of claim 10, wherein the first portion of the phase-change material of the memory cell is amorphized after it is heated by the first write pulse and subsequently quenched.

12. The memory cell device of claim 10, wherein the second portion of the phase-change material of the memory cell is amorphized after it is heated by the second write pulse and subsequently quenched.

13. The memory cell device of claim 10, wherein the phase-change material experiences material expansion of less than 15% during the phase change.

14. The memory cell device of claim 10, wherein setting the phase-change material of the memory cell is setting the material to a crystalline state, and wherein resetting the phase-change material of the memory cell is setting the material to an amorphous.

15. The memory cell device of claim 10, the phase-change material is selected from a group comprising GeSbTe, AgInSbTe, GeSb, GaSb, and chalcogenide alloys.

16. A memory device comprising:

a plurality of phase-change memory cells each having phase-change material that can be set and reset;

a write pulse generator that generates at least first and second write pulse signals for a single reset operation; and

a distribution circuit for distributing the first and second write pulse signals for a single reset operation to a selected memory cell;

wherein the first write pulse signal heats and melts a first portion of the phase-change material of the selected memory cell, and wherein the second write pulse signal heats and melts a second portion of the phase-change material of the selected memory cell.

17. The memory device of claim 16, wherein the write pulse generated is directed through the phase-change material thereby heating up the material.

18. The memory device of claim 16, the phase-change material is selected from a group comprising GeSbTe, AgInSbTe, GeSb, GaSb, and chalcogenide alloys.

19. The memory device of claim 16 configured in a random access memory device.

20. The memory device of claim 16, wherein the phase-change memory cells, the write pulse means, and the sensor means are all integrated in a single chip.