Non-volatile latch circuit

• US 7,031,189 B2
• Filed: 05/07/2003
• Issued: 04/18/2006
• Est. Priority Date: 05/10/2002
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pascucci, Luigi
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US10/434,395
• Publication Number:
  US 20040008539A1
• Time in Patent Office: 1,077 Days
• Field of Search: 365/185.07, 365/185.08, 365/185.09, 365/185.28, 365/185.26, 365/185.03
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A memory cell includes a volatile circuit operable to store first data, and a nonvolatile circuit coupled to the volatile circuit and operable to store second data. The volatile circuit is operable to program the nonvolatile circuit with the first data, and the nonvolatile circuit is operable to program the volatile circuit with the second data.

Claims

1. A non-volatile latch circuit, comprising:

a first, volatile information-storage element;

a second, non-volatile information-storage element electrically programmable, associated with the first information-storage element;

first circuit means activatable for operatively coupling the second information-storage element to the first information-storage element, the first circuit means being activated for loading into the first information-storage element an information stored in the second information-storage element,

second circuit means associated with the first information-storage element for programming the first information-storage element in a select state;

third circuit means associated with the second information-storage element and driven by the first information-storage element for selectively enabling the programming of the second information-storage element depending on the state of the first information-storage element.

2. The non-volatile latch circuit according to claim 1, further comprising fourth circuit means for directly accessing the second information-storage element from outside the non-volatile latch.

3. The non-volatile latch circuit according to claim 1, in which the second information-storage element includes a first electrode and a second electrode, the first electrode being selectively couplable to the first information-storage element or to a first programming potential through the first and the third circuit means, respectively, the second electrode being adapted to receiving a second programming potential or a read potential.

4. The non-volatile latch circuit according to claim 1, in which the second information-storage element includes a floating-gate MOS transistor.

5. The non-volatile latch circuit according to claim 1, in which the second information-storage element includes a MOS transistor in which the first electrode and the second electrode exchange the function of source electrode and drain electrode in the operations of reading and programming of the transistor.

6. The non-volatile latch circuit according to claim 4, in which the first and the third circuit means are adapted to leave the first electrode floating, and the second electrode is adapted to receive an erase potential of the non-volatile storage element.

7. A method of storing a binary information in the non-volatile latch circuit realized according to claim 1, characterized by comprising a phase of setting the first information-storage element in a state corresponding to the information to be stored, through said second circuit means.

8. The method according to claim 7 for storing the binary information in non-volatile way, further comprising a following phase of applying programming potentials to the second information-storage element, the third circuit means enabling or not enabling the programming of the second information-storage element depending on the state set in the first information-storage element.

9. The method according to claim 8, comprising furnishing to the first information-storage element the binary information to be stored only during said phase of setting the first information-storage element.

10. A register comprising a plurality of binary information storage units, characterized in that said information storage units include non-volatile latch circuits according to claim 1.

11. A redundancy circuit for a semiconductor memory, comprising a plurality of registers each one adapted to store an address of a defective memory location to be functionally replaced by a redundancy memory location associated with the register, characterized in that the registers are realized according claim 10.

12. A semiconductor memory comprising the redundancy circuit realized according to claim 11.

13. The memory according to claim 12, in which:

a first selective-connection circuit allows selectively connecting lines of an address bus of the memory to the second circuit means of the non-volatile latches of the registers, so as to exploit the lines of the address bus for bringing a data word intended for setting in each register;

a second selective-connection circuit allows selectively connecting lines of a data bus of the memory to command lines of the second circuit means of the non-volatile latches of the registers, so as to exploit the lines of the data bus for selectively commanding the activation of the second circuit means for each register.

14. An integrated circuit comprising a configurable circuit structure and a control circuit of the configurable circuit structure, said control circuit comprising at least one register for storing a selected configuration for the configurable circuit structure, characterized in that said register is realized according to claim 10.

15. A memory cell, comprising:

a volatile circuit operable to store first data;

a nonvolatile circuit operable to store second data;

an inverter coupled between the volatile circuit and the nonvolatile circuit and operable to program the nonvolatile circuit with the first data; and

wherein the nonvolatile circuit is operable to program the volatile circuit with the second data.

16. The memory cell of claim 15 wherein the volatile circuit is operable to receive the first data from a source other than the nonvolatile circuit.

17. The memory cell of claim 15 wherein the volatile circuit comprises a pair of cross coupled inverters.

18. The memory cell of claim 15 wherein the nonvolatile circuit is operable to store a single data bit.

19. The memory cell of claim 15 wherein the nonvolatile circuit is operable to store multiple bits of data.

22. The memory cell of claim 15 wherein the inverter is coupled between the nonvolatile circuit and a first node of the volatile circuit, and a transistor is coupled between the nonvolatile circuit and a second node of the volatile circuit.

23. The memory cell of claim 15 wherein the inverter comprises a transistor having a control node coupled to the volatile circuit and an output node coupled to the nonvolatile circuit.

20. An integrated circuit, comprising:

a memory cell, comprising,

a volatile circuit operable to store first data,

a nonvolatile circuit operable to store second data,

an inverter coupled between the volatile circuit and the nonvolatile circuit and operable to program the nonvolatile circuit with the first data, and

wherein the nonvolatile circuit is operable to program the volatile circuit with the second data.

21. An electronic system, comprising:

an integrated circuit, comprising,

a memory cell, comprising,

a volatile circuit operable to store first data,

a nonvolatile circuit operable to store second data,

an inverter coupled between the volatile circuit and the nonvolatile circuit and operable to program the nonvolatile circuit with the first data, and

wherein the nonvolatile circuit is operable to program the volatile circuit with the second data.