Method and apparatus for rapidly storing data in memory cell without voltage loss

• US 7,031,202 B2
• Filed: 12/22/2003
• Issued: 04/18/2006
• Est. Priority Date: 05/29/2003
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Jae-Jin, Yoon, Seok-Cheol
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/744,257
• Publication Number:
  US 20040240304A1
• Time in Patent Office: 848 Days
• Field of Search: 365/189.09, 365/207
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

The present relates to a memory device; and, more particularly, to an apparatus and a method for preventing a loss of reliability of data, which are stored in memory cell, at the time of restoring and writing the data. The semiconductor memory device according to the present invention comprises: a high voltage generator for boosting an external voltage level and then for producing a first high voltage level; a pumping control signal generator for issuing a pumping control signal, which is activated in a restore section and a write section, in response to a command signal; a pumping unit for outputting the first high voltage level from the high voltage generator or for boosting the high voltage level in order to generate a second high voltage plus level in response to the pumping control signal from the pumping control signal generator, wherein the second high voltage plus level is higher than the first high voltage level; and a word line driver for driving the word line WL using the first high voltage level and for driving the word line WL using the second high voltage plus level from the pumping unit in the restore and write sections.

Claims

1. A semiconductor memory device comprising:

a high voltage generating means for boosting an external voltage level and then for producing a first high voltage level;

a pumping control signal generating means for issuing a pumping control signal, which is activated in a restore section and a write section, in response to a command signal;

a pumping unit for outputting the first high voltage level from the high voltage generating means or for boosting the high voltage level in order to generate a second high voltage plus level in response to the pumping control signal from the pumping control signal generator, wherein the second high voltage plus level is higher than the first high voltage level; and

a word line driving means for driving the word line WL using the first high voltage level and for driving the word line WL using the second high voltage plus level from the pumping unit in the restore and write sections.

2. The semiconductor memory device as recited in claim 1, wherein the word line driving means is driven by the first high voltage level and activates the word line in the first high voltage level in memory operation sections in which memory cell data are induced on a bit line and the induced cell data are amplified and wherein the word line driving means is driven by the second high voltage level and activates the word line in the second high voltage level in a memory operation section in which memory cell data on the bit line are restored in a memory cell.

3. The semiconductor memory device as recited in claim 1, wherein the word line driving means is driven by the first high voltage level and activates the word line in the first high voltage level in memory operation sections in which memory cell data are induced on a bit line and the induced cell data are amplified and wherein the word line driving means is driven by the second high voltage level and activates the word line in the second high voltage level in a write operation section in which an external input data on the bit line are stored in a memory cell in response to a write command.

4. The semiconductor memory device as recited in claim 1, wherein the pumping unit includes:

a power supply formed between an output terminal of the high voltage generating means and a driving voltage terminal of the word line driver;

a switching means for turning on or off the power supply in the restore or write section; and

a capacitor for increasing a first high voltage level of the switching means to the second high voltage level in the restore or write section.

5. The semiconductor memory device as recited in claim 4, wherein the pumping control signal generating means includes:

a control signal generating means for producing a control signal, which are activated in a precharge section and the write section, in response to the command signal;

a switching control signal generating means for buffering the control signal and for controlling the switching means; and

a pumping signal generating means for buffering and delaying the control signal.

6. The semiconductor memory device as recited in claim 5, wherein the switching means includes a MOS transistor which transfers the power supply voltage in response to the switching control signal.

7. The semiconductor memory device as recited in claim 5, wherein the pumping unit includes a MOS transistor which has a source and drain, which are coupled to the pumping signal, and a gate receiving an output signal of the switching means.

8. The semiconductor memory device as recited in claim 1, wherein the switching control signal and the pumping signal are activated in the restore and write sections and wherein the switching control signal is activated before the pumping signal is activated.

9. A method for driving a semiconductor memory device comprising the steps of:

activating a word line in a first high voltage level in response to an active command and inducing a fine voltage of cell data on the bit line, wherein the first high voltage level is higher than an external voltage level;

amplifying the fine voltage on the bit line;

activating the word line in a second high voltage level and restoring the amplified voltage on the bit line, wherein the second high voltage level is higher than the first high voltage level; and

non-activating the word line in response to a precharge command and precharging the bit line.

10. The method for driving a semiconductor memory device as recited in claim 9, wherein the step of writing the voltage level on the bit line in a memory cell includes the step of inverting the amplified voltage level on the bit line.

11. A semiconductor memory device comprising:

a driving voltage generating means for producing a driving voltage level using an external voltage level;

a pumping control signal generating means for producing a pumping control signal, which is activated in a restore section and a write section, in response to a command signal;

a pumping means for transferring the driving voltage level from the driving voltage generating means or for boosting the external voltage level in order to output a high voltage level which is higher than the external voltage level; and

a bit line sense amplifier for receiving the external voltage level or the high voltage level from the pumping means and amplifying the bit line voltage of a selected memory cell.

12. The semiconductor memory device as recited in claim 11, wherein the bit line sense amplifier receives the external voltage in which memory cell data are induced on a bit line and the induced cell data are amplified and wherein the bit line sense amplifier receives the high voltage level in a memory operation section in which memory cell data on the bit line are restored in a memory cell.

13. The semiconductor memory device as recited in claim 11, wherein the bit line sense amplifier receives the external voltage level in memory operation sections in which memory cell data are induced on a bit line and the induced cell data are amplified and wherein the bit line sense amplifier receives the high voltage level in a write operation section in which an external input data on the bit line are stored in a memory cell in response to a write command.

14. The semiconductor memory device as recited in claim 11, wherein the pumping unit includes:

a power supply formed between an output terminal of the driving voltage generating means and an driving voltage terminal of the bit line sense amplifier;

a switching means for turning on or off the power supply in the restore or write section; and

a pumping unit for increasing an output level of the switching means in the restore or write section.

15. The semiconductor memory device as recited in claim 14, wherein the pumping control signal generating means includes:

a control signal generating means for producing a control signal, which are activated in a precharge section and the write section, in response to the command signal;

a switching control signal generating means for buffering the control signal and for controlling the switching means; and

a pumping signal generating means for buffering and delaying the control signal.

16. The semiconductor memory device as recited in claim 15, wherein the switching means includes a MOS transistor which transfers the power supply voltage in response to the switching control signal.

17. The semiconductor memory device as recited in claim 15, wherein the pumping unit includes a NMOS transistor which has a source and drain, which are coupled to the pumping signal, and a gate receiving an output signal of the switching means.

18. The semiconductor memory device as recited in claim 15, wherein the switching control signal and the pumping signal are activated in the restore and write sections and wherein the switching control signal is activated before the pumping signal is activated.

19. A method for driving a semiconductor memory device comprising the steps of:

amplifying a voltage level corresponding to a cell data, which is induced on a bit line, using an external voltage level;

restoring the amplified voltage level on the bit line using a high voltage level in response to a write recovery operation, which is higher than the external voltage level; and

non-activating the word line and precharging the bit line.

22. The method for driving a semiconductor memory device as recited in claim 19, further comprising:

inversing the amplified voltage level on the bit line using the high voltage level in order to correspond to an input data in response to a write command.

20. A method for driving a semiconductor memory device comprising the steps of:

amplifying a voltage level corresponding to a cell data, which is induced on a bit line, using an external voltage level while a word line is activated by a first high voltage level;

applying a voltage level corresponding to an input data to the bit line in response to a write command;

writing the amplified voltage level on the bit line while a word line is activated by a second high voltage level, wherein the second high voltage level is higher than the first high voltage level; and

non-activating the word line and precharging the bit line.

21. The method for driving a semiconductor memory device as recited in claim 20, wherein the step of writing the voltage level on the bit line in a memory cell includes the step of inverting the amplified voltage level on the bit line.