Method of measuring threshold voltage for a NAND flash memory device

• US 7,031,210 B2
• Filed: 06/29/2004
• Issued: 04/18/2006
• Est. Priority Date: 11/18/2003
• Status: Active Grant

• Current Assignee: SK Hynix Inc., STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Jin Su, Kim, Doe Cook
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Graham, Kretelia
• Application Number:
  US10/879,540
• Publication Number:
  US 20050105333A1
• Time in Patent Office: 658 Days
• Field of Search: None
• US Class Current: 365/201
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

Provided is a method of measuring threshold voltages in a NAND flash memory device. In the method, a test voltage is applied to a wordline of selected memory cells to measure a distribution profile of threshold voltages of memory cells. A voltage summing up a pass voltage and an operation voltage is applied to wordlines of deselected cells. The operation voltage is applied to a well and a common source line. A voltage summing up a precharge voltage and the operation voltage is applied to a bitline. After then, a voltage variation on the bitline can be detected to measure a threshold voltage of a memory cell. A negative threshold voltage can be measured by applying a positive voltage with reference to a voltage, as the threshold voltage of the memory cell, set by subtracting the operation voltage from the test voltage in accordance with the bitline voltage variation.

Claims

1. A method of measuring threshold voltages in a NAND flash memory device including a plurality of cell strings each having a plurality of memory cells connected in series, common drain nodes of the cell strings, common source nodes of the cell strings, wordlines for selecting the memory cells, and a well of a semiconductor substrate in which the memory cell is formed, the method comprising the steps of:

applying an operation voltage to the well and the common source nodes;

applying a test voltage, which is assigned to measure a threshold voltage, to the wordline of a selected memory cell;

applying a voltage, which is obtained by summing up a pass voltage and the operation voltage, to the wordlines of deselected memory cells;

applying a voltage, which is obtained by summing up a precharge voltage and the operation voltage, to the common drain node; and

detecting a variation of voltage at the common drain node.

2. The method according to claim 1, wherein the test voltage is 0V through 10V;

the operation voltage is 3V through 4V;

the pass voltage is 4V through 6V; and

the precharge voltage is 1V through 2V.

3. The method according to claim 2, wherein the voltage obtained by summing up the precharge voltage and the operation voltage is applied to the common drain node through a virtual power input terminal to initiate the common drain node.

4. A method of measuring threshold voltages in a NAND flash memory device including a plurality of cell strings each having a plurality of memory cells connected in series, a plurality of bitlines connected to common drain nodes of the cell strings, a common source line connected to common source nodes of the cell strings, wordlines intersecting the bitlines so as to select the memory cells, and a well of a semiconductor substrate in which the memory cell is formed, the method comprising the steps of:

applying an operation voltage to the well;

applying a voltage, which is obtained by summing up a precharge voltage and the operation voltage, to the bitline, applying a test voltage to a selected wordline, applying a voltage, which is obtained by summing up a pass voltage and the operation voltage, to deselected wordlines, and applying the operation voltage to the common source line; and

identifying, after detecting a voltage variation of the bitline during a read operation, a threshold voltage of a selected memory cell as a value obtained by subtracting the operation voltage from the test voltage when there is no voltage variation on the bitline, while increasing the test voltage by a predetermined level when the voltage of the bitline decreases.

5. The method according to claim 4, wherein the test voltage is 0V through 10V;

the operation voltage is 3V through 4V;

the pass voltage is 4V through 6V; and

the precharge voltage is 1V through 2V.

6. The method according to claim 5, wherein the voltage obtained by summing up the precharge voltage and the operation voltage is applied to the common drain node through a virtual power input terminal to initiate the common drain node.