Digital multilevel memory system having multistage autozero sensing

• US 7,031,214 B2
• Filed: 12/11/2002
• Issued: 04/18/2006
• Est. Priority Date: 01/14/1999
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US10/317,409
• Publication Number:
  US 20030103406A1
• Time in Patent Office: 1,224 Days
• Field of Search: 365/206, 365/208, 365/210, 365/207, 365/185.11, 365/185.12
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.

Claims

1. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells, selected memory cells being placed in a current sensing mode during a read or verify operation, and

a plurality of autozero current sense amplifiers, each autozero sense amplifier being coupled to a group of said memory subarrays, the autozero sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays.

2. The data storage system of claim 1 wherein the memory cells are multilevel memory cells.

3. The data storage system of claim 2 wherein the memory cells are nonvolatile memory cells.

4. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells, selected memory cells being placed in a current sensing mode during a read or verify operation, and

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays.

5. The data storage system of claim 4 wherein the memory subarrays further comprise a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers.

6. The data storage system of claim 4 wherein the memory cells are multilevel memory cells.

7. The data storage system of claim 6 wherein the memory cells are nonvolatile memory cells.

8. The data storage system of claim 4 wherein the memory cells are nonvolatile memory cells.

9. A data storage system comprising:

a plurality of memory subarrays, each memory subarray comprising a plurality of data memory cells, a plurality of reference memory cells and a plurality of subarray bitlines, each memory cell being configurable to store one of the plurality of signal levels and being coupled to one of said bitlines;

a plurality of local sense amplifiers, each of said plurality of local sense amplifiers being coupled to a corresponding one of said plurality of memory subarrays and being selectively coupled to said subarray bitlines in said memory subarray;

a plurality of global bitlines, each local sense amplifier being coupled to one of said plurality of global bitlines, the plurality of global bitlines being arranged in a crossed configuration; and

a plurality of global sense amplifiers, each global sense amplifier being coupled to a group of said global bitlines.

10. The data storage system of claim 9 wherein the memory cells are nonvolatile memory cells.

11. The data storage system of claim 10 wherein the memory cells are multilevel memory cells.

12. The data storage system of claim 9 wherein the memory cells are multilevel memory cells.

13. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of data memory cells and a plurality of reference memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers.

14. The data storage system of claim 13 wherein the plurality of memory subarrays are arranged in segments.

15. The data storage system of claim 13 wherein the memory cells are multilevel memory cells.

16. The data storage system of claim 13 wherein the memory cells are nonvolatile memory cells.

17. The data storage system of claim 16 wherein the nonvolatile memory cells are multilevel memory cells.

18. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers,

wherein the plurality of memory subarrays are arranged in segments,

wherein the segments include data memory cells and reference memory cells.

19. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers,

wherein the autozero local sense amplifier is a current sensing autozero local sense amplifier, and the autozero global sense amplifier is a voltage sensing sense amplifier.

20. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers,

wherein the autozero local sense amplifier is a current sensing sense amplifier and the global sense amplifier is a current sensing sense amplifier.

21. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers,

wherein the local autozero sense amplifier is a voltage sensing sense amplifier, and the global sense amplifier is a current sensing sense amplifier.

22. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers,

wherein the plurality of memory subarrays are arranged in pages and each page includes data memory cells and reference memory cells.

23. A data storage system comprising:

a plurality of memory arrays, each memory array comprising;

a plurality of memory subarrays, each memory subarray including a plurality of memory cells,

a plurality of autozero local sense amplifiers, each autozero local sense amplifier being disposed adjacent to and coupled to a group of said memory subarrays, the autozero local sense amplifier reading the contents of the memory cells within the corresponding group of memory subarrays, and

a plurality of autozero global sense amplifiers, each autozero global sense amplifier being coupled to a group of said autozero local sense amplifiers,

wherein the plurality of memory subarrays include memory cells arranged in rows, a group of said memory cells being reference memory cells.

24. A memory system comprising:

a plurality of differential sense amplifiers, each differential sense amplifier having first and second inputs, and having an output for generating a data signal indicative of a comparison between signals applied to said first and second inputs; and

a plurality of memory segments, each memory segment including a plurality of columns of memory cells, a plurality of column switches, a plurality of reference switches, and a segment switch, each column switch coupled between a corresponding column and the segment switch, the segment switch coupled between the column switches and the first input of the differential sense amplifier, each reference switch being coupled between a corresponding column of memory cells and the second input of a corresponding one of said differential sense amplifiers, one of said memory segments storing reference valves in a group of said columns of memory cells.

25. The memory system of claim 24 wherein the reference switches of said one of said memory segments storing reference values are enabled and the column switches of another one of said memory segments are enabled to read, program, or verify memory cells in said another one of said memory segments.