Semiconductor device having a mode of functional test

• US 7,031,864 B2
• Filed: 04/23/2001
• Issued: 04/18/2006
• Est. Priority Date: 07/18/2000
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Matsui, Katsuaki
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): West, Jeffrey R
• Application Number:
  US09/839,671
• Publication Number:
  US 20020010559A1
• Time in Patent Office: 1,821 Days
• Field of Search: 702/79, 702/89, 702117-120, 702176-178, 714/724, 714/726, 714/731, 714/733, 714/734, 716/6, 716/17, 324/532, 324/534
• US Class Current: 702/117
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A semiconductor device including a first signal path for guiding an input signal from a first pad to an input terminal of a macro cell; a second signal path for guiding a clock from a second pad to a clock input terminal of the macro cell; a third signal path for guiding an output signal from a signal output terminal of the macro cell to a third pad; and a fourth signal path for receiving the clock from the first signal path and guiding the clock to a fourth pad. It is possible to eliminate wiring delay by measuring the time from when the input signal and the clock are supplied by the first and second pads until the output signal is output by the third pad, and the time from when the clock is supplied to the second path until it is output by the fourth pad.

Claims

1. A semiconductor device having an access time measuring test mode, comprising:

a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to said input signal;

a first signal path for guiding a test input signal, which has been supplied to a first pad, from said first pad to a signal input terminal of said circuit block;

a second signal path for guiding a test clock, which has been supplied to a second pad, from said second pad to a clock input terminal of said circuit block;

a third signal path for guiding a test output signal, which has been output from a signal output terminal of said circuit block, from said signal output terminal to a third pad; and

a fourth signal path for guiding said test clock, which is input to said clock input terminal, from said clock input terminal to a fourth pad,

wherein said third and fourth signal paths are formed so that wiring delay time of said third and fourth signal paths are substantially equal,

wherein said fourth signal path has provided therein a first selector, responsive to a mode of a selection signal, that selectively supplies a prescribed signal or said test clock directly to said fourth pad, a first wiring that directly connects said clock input terminal of said circuit block to an input terminal of said first selector, and a second wiring that directly connects an output terminal of said first selector to said fourth pad,

wherein said third signal path has provided therein a second selector which during a normal operation supplies a second prescribed signal other than said test output signal to said third pad and which during a test operation supplies said test output signal to said third pad, a third wiring that directly connects said signal output terminal of said circuit block to an input terminal of said second selector, and a fourth wiring that directly connects an output terminal of said second selector to said third pad, and

wherein said third and fourth signal paths are provided so that a difference of timings from when said test clock is output at said fourth pad to when said test output signal is output at said third pad is indicative of an access time of said circuit block.

2. The semiconductor device according to claim 1, wherein said first signal path has provided therein a third selector which during the normal operation supplies an output signal from a preceding circuit block to said signal input terminal of said circuit block, and which during the test operation supplies said test input signal to said signal input terminal of said circuit block.

3. The semiconductor device according to claim 1, wherein said second signal path has provided therein a third selector which during the normal operation supplies a normal clock to said clock input terminal of said circuit block, and which during the test operation supplies said test clock to said clock input terminal of said circuit block.

4. The semiconductor device according to claim 1, wherein the wiring delay time of said third and fourth signal paths are set to be substantially equal whereby a sum of lengths of said first and second wirings is set to be substantially the same as a sum of lengths of said third and fourth wirings.