Methods and circuitry for interconnecting data and clock busses of live backplane circuitry and input/output card circuitry, and methods and circuitry for isolating capacitanes of a live backplane from the capacitanes of at least one input/output card

• US 7,032,051 B2
• Filed: 12/11/2001
• Issued: 04/18/2006
• Est. Priority Date: 12/11/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Reay, Robert L., Ziegler, John H.
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): Phan, Raymond N
• Application Number:
  US10/013,893
• Publication Number:
  US 20020091887A1
• Time in Patent Office: 1,589 Days
• Field of Search: 710300-306, 710 8- 19, 710 2- 3, 710/105, 710/106, 710/110, 710/310, 710/311, 710313-317, 713 1- 2, 713/330
• US Class Current: 710/301
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004

Abstract

Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a “hot-swappable” fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card.

Claims

1. A method for interconnecting a live backplane having a data bus and a clock bus to at least a first two-wire I/O card having a data bus and a clock bus using interconnection circuitry, said method comprising:

monitoring said backplane data bus and said backplane clock bus to determine a first condition indicative of whether said backplane may be interconnected with said first I/O card;

monitoring said I/O card data bus and said I/O card clock bus to determine a second condition indicative of whether said first I/O card may be interconnected with said backplane; and

interconnecting said backplane with said first I/O card when said first and second conditions have been met.

2. The method of claim 1, wherein said first condition occurs when said backplane data bus exhibits a signal that transitions from LOW-to-HIGH while said backplane clock bus is exhibiting a HIGH signal.

3. The method of claim 1, wherein said first condition occurs when said backplane data bus and said backplane clock bus both exhibit HIGH signals for a predetermined period of time.

4. The method of claim 1, wherein said second condition occurs when said first I/O card data bus and said first I/O card clock bus exhibit HIGH signals.

5. The method of claim 1 further comprising:

prior to having met said first and second conditions, charging said backplane busses and said first I/O card busses to a predetermined voltage level; and

ceasing said charging when said first and second conditions are met.

6. The method of claim 1 further comprising:

preventing said monitoring of said backplane busses and said first I/O card busses when said interconnection circuitry has a supply voltage level below a predetermined voltage level.

7. The method of claim 1, wherein said interconnecting comprises closing a first plurality of switches to interconnect said backplane data bus to said first I/O card data bus and to interconnect said backplane clock bus to said first I/O card clock bus.

8. The method of claim 1, wherein said interconnecting comprises providing bias current to a plurality of amplifiers to interconnect said backplane data bus to first I/O card data bus and to interconnect said backplane clock bus to said first I/O card clock bus.

9. The method of claim 1 further comprising:

after said interconnecting occurs, disconnecting said backplane from said first I/O card when said interconnection circuitry has a supply voltage level that falls below a predetermined voltage level; and

preventing said monitoring of said backplane busses and said first I/O card busses until said supply voltage level rises above said predetermined voltage level.

10. An interconnection circuit that connects a live backplane having a backplane data bus and a backplane clock bus to at least a first two-wire I/O card having a first I/O card data bus and a first I/O card clock bus, said circuit comprising:

buffer circuitry coupled between said backplane data bus and said first I/O card data bus, and coupled between said backplane clock bus and said first I/O card clock bus; and

monitoring circuitry that monitors said backplane data and clock busses for a first condition, and said I/O card data and clock busses for a second condition, and causing said buffer circuitry to couple said backplane and I/O card data busses together and to couple said backplane and I/O card clock busses together when said first and second conditions are met.

11. The circuit of claim 10 further comprising:

under voltage lockout circuitry that prevents said monitoring circuitry from monitoring said backplane busses and said first I/O card busses when an interconnection circuit supply voltage level is below a predetermined voltage level.

12. The circuit of claim 10 further comprising:

a first plurality of switches coupled to said buffer circuitry and configured to OPEN and CLOSE said switches based on a signal provided by said monitoring circuitry, said switches, when CLOSED, cause said backplane and I/O card busses to couple to said buffer circuitry.

13. The circuit of claim 10 further comprising:

precharge circuitry that is coupled between said backplane busses and said first I/O card busses; and

a second plurality of switches coupled to said precharge circuitry, said second switches, when CLOSED, cause said precharge circuitry to apply a predetermined voltage to said backplane busses and to said first I/O card busses.

14. The circuit of claim 10, wherein said first condition occurs when said backplane data bus exhibits a signal that transitions from LOW-to-HIGH while said backplane clock bus is exhibiting a HIGH signal.

15. The method of claim 10, wherein said first condition occurs when said backplane data bus and said backplane clock bus both exhibit HIGH signals for a predetermined period of time.

16. The method of claim 10, wherein said second condition occurs when said first I/O card data bus and said first I/O card clock bus exhibit HIGH signals.

17. The circuit of claim 10, wherein said buffer circuitry comprises:

cross-coupled circuitry that isolates the capacitance associated with the backplane busses from the capacitance associated with the first I/O card busses.

18. The circuit of claim 11, wherein said under voltage lockout circuitry is configured to cause said monitoring circuitry to disconnect said backplane busses from said first I/O card busses when said interconnection circuit supply voltage level falls below a second predetermined voltage level.

19. The circuit of claim 13, wherein said monitoring circuitry causes said second switches to OPEN and remain OPEN when said first and second conditions are met.

20. The circuit of claim 13, wherein said monitoring circuitry causes second switches to be CLOSED until both said first and second conditions are met.

21. The circuit of claim 17, wherein said cross-coupled circuitry drives a signal between said backplane data bus and said first I/O card data bus.

22. The circuit of claim 17, wherein said cross-coupled circuitry drives a signal between said backplane clock bus and said first I/O card clock bus.

23. A method for driving at least one signal between a backplane bus and at least a first I/O card bus, said method comprising:

isolating the capacitance associated with said backplane bus from the capacitance associated with said first I/O card bus;

driving said at least one signal from said backplane bus to said first I/O card bus at a level that need only overcome said backplane capacitance; and

driving said at least one signal from said first I/O card bus to said backplane bus at a level that need only overcome said first I/O card capacitance.

24. The method of claim 23 further comprising:

maintaining a predetermined differential voltage level between a backplane bus voltage level and a first I/O card bus voltage level when said signal is driven from said backplane bus to said first I/O card bus.

25. The method of claim 23 further comprising:

maintaining a predetermined differential voltage level between a backplane bus voltage level and a first I/O card bus voltage level when said signal is driven from said first I/O card bus to said backplane bus.

26. The method of claim 23, wherein said isolating comprises providing high-speed signal propagation between said backplane bus and said first I/O card bus.

27. The method of claim 23, wherein said isolating comprises isolating the capacitance associated with said first I/O card bus from the capacitance associated with at least a second I/O card bus.

28. The method of claim 23, wherein said isolating comprises isolating the capacitance associated with at least a second I/O card bus from the capacitance associated with said backplane bus.

29. The method of claim 23 further comprising:

disabling said driving of said at least one signal from said backplane bus to said first I/O card bus when said at least one signal is transitioning from LOW-to-HIGH.

30. The method of claim 23 further comprising:

disabling said driving of said at least one signal from said first I/O card bus to said backplane bus when said at least one signal is transitioning from LOW-to-HIGH.

31. The method of claim 23 further comprising:

providing current to said backplane bus and said first I/O card bus when said at least one signal is transitioning from LOW-to-HIGH.

32. The method of claim 23 further comprising:

when voltages on said backplane bus and said first I/O card bus are rising, regulating the voltage on either said backplane bus and said first I/O card bus when the voltage differential of the two busses exceeds a predetermined differential voltage level such that the voltages on both said backplane bus and said first I/O card bus rise at a substantially similar rate.

33. An interconnection circuit that drives at least one signal between a backplane bus and at least a first I/O card bus, said circuit comprising:

backplane driving circuitry configured to isolate the capacitance associated with said backplane bus from the capacitance associated with said first I/O card bus, and to drive said signal from said backplane bus to said first I/O card bus at a level that need only overcome said backplane capacitance; and

first I/O card driving circuitry configured to isolate the capacitance associated with said first I/O card bus from the capacitance associated with said backplane bus, and to drive said signal from said first I/O card bus to said backplane bus at a level that need only overcome said first I/O card capacitance.

34. The circuit of claim 33, wherein said backplane driving circuitry comprises:

a backplane amplifier coupled to said backplane bus;

a backplane transistor coupled to said first I/O card bus and said backplane amplifier, said backplane amplifier configured to drive said backplane transistor in response to a signal on said backplane bus; and

a backplane voltage source coupled between said backplane amplifier and said first I/O card bus.

35. The circuit of claim 33, wherein said first I/O card driving circuitry comprises:

an I/O card amplifier coupled to said first I/O card bus;

an I/O card transistor coupled to said backplane bus and to said I/O card amplifier, said I/O card amplifier configured to drive said first I/O card transistor in response to a signal on said first I/O card bus; and

an I/O card voltage source coupled between said I/O card amplifier and said backplane bus.

36. The circuit of claim 33, wherein said backplane driving circuitry and said first I/O card driving circuitry are interconnected in a cross-coupled configuration.

37. The circuit of claim 33, wherein said backplane driving circuitry is a transistor.

38. The circuit of claim 33, wherein said first I/O card driving circuitry is a transistor.

39. The circuit of claim 33, wherein said backplane driving circuitry comprises

a first plurality of transistors coupled together and configured to drive said signal from said backplane bus to said first I/O card bus.

40. The circuit of claim 33, wherein said first I/O card driving circuitry comprises:

a second plurality of transistors coupled together and configured to drive said signal from said first I/O card bus to said backplane bus.

41. The circuit of claim 33 further comprising:

current boost circuitry configured to provide current to said backplane bus and to said first I/O card bus when said at least one signal is transitioning from LOW-to-HIGH.

42. The circuit of claim 33 further comprising:

control circuitry that disables said backplane driving circuitry and said first I/O card driving circuitry when said at least one signal is transitioning from LOW-to-HIGH.

43. The circuit of claim 34, wherein said backplane driving circuitry is configured to drive said at least one signal such that a backplane bus voltage level and a first I/O card bus voltage level differ at most by a predetermined voltage level set by said backplane voltage source.

44. The circuit of claim 34, wherein said backplane voltage source prevents said backplane driving circuitry from driving said at least one signal when said first I/O card driving circuitry is driving said at least one signal.

45. The circuit of claim 35, wherein said first I/O card driving circuitry is configured to drive said at least one signal such that a first I/O card bus voltage level and a backplane bus voltage level differ at most by a predetermined voltage level set by said I/O card voltage source.

46. The circuit of claim 35, wherein said first I/O card voltage source prevents said first I/O card driving circuitry from driving said at least one signal when said backplane driving circuitry is driving said at least one signal.

47. The circuit of claim 39 further comprising:

a backplane current source coupled to at least one of said first plurality of transistors and configured to assist in driving said signal from said backplane bus to said first I/O card bus.

48. The circuit of claim 40 further comprising:

a first I/O card current source coupled to at least one of said second plurality of transistors and configured to assist in driving said signal from said first I/O card bus to said backplane bus.

49. An interconnection circuit that connects a live backplane having a backplane data bus and backplane clock bus to at least a first I/O card having a first I/O card data bus and a first I/O card clock bus, said circuit comprising:

buffer circuitry coupled between said backplane data bus and said I/O card data bus, and coupled between said backplane clock bus and said I/O card clock bus, wherein said buffer circuitry comprises cross-coupled circuitry that isolates the capacitance associated with the backplane busses from the capacitance associated with the first I/O card busses;

interconnection circuitry operative to selectively couple said backplane data and clock busses and said I/O card data and clock busses to said buffer circuitry; and

address circuitry that causes said interconnection circuitry to couple said backplane data and clock busses and said I/O card data and clock busses to said buffer circuitry when said address circuitry receives a predetermined signal.

50. The circuit of claim 49, wherein said address circuitry comprises:

a plurality of address pins that, when connected, determine a digital address for said interconnection circuit.

51. The circuit of claim 49, wherein said address circuitry comprises:

a decoder that decodes data signals provided by said backplane data bus.

52. The circuit of claim 49, wherein said cross-coupled circuitry is first cross-coupled circuitry, which drives a signal between said backplane data bus and said first I/O card data bus.

53. The circuit of claim 49, wherein said cross-coupled circuitry is second cross-coupled circuitry, which drives a signal between said backplane clock bus and said first I/O card clock bus.