Method and apparatus for booting a microprocessor

• US 7,032,106 B2
• Filed: 12/27/2001
• Issued: 04/18/2006
• Est. Priority Date: 12/27/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Computer Network Technology Corp. (Broadcom, Inc.)
• Inventors: Mathur, Akshay, Horanzy, Joseph
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): Stoynov, Stefan
• Application Number:
  US10/026,707
• Publication Number:
  US 20030126424A1
• Time in Patent Office: 1,573 Days
• Field of Search: 713/2, 713/1
• US Class Current: 713/2
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A method and system for bootstrapping a processor from a volatile memory device connected to the processor is disclosed. The first processor is bootstrapped from flash device. The reset lines of the second processor are asserted. The boot code for the second processor is loaded from the flash device into the volatile memory device. The reset lines of the second processor are de-asserted, wherein the processor then boots from the boot code stored in the volatile memory device. The same boot-strapping method can be extended to multi-drop systems where number of secondary processor can be more than one. A switchable means for the second processor to boot from volatile memory as described or from flash memory. A method also describes a mechanism to boot from synchronous volatile memory devices.

Claims

1. A method for using a first processor to bootstrap a second processor from a synchronous volatile memory device connected to the second processor, comprising the steps of:

bootstrapping the first processor from flash device;

asserting reset lines of the second processor;

loading boot code for the second processor from the flash device into the volatile memory device;

de-asserting the reset lines of the second processor,

preventing the second processor from attempting to read the volatile memory device while a clock signal from the second processor stabilizes after reset; and

providing the clock signal from the second processor to the synchronous volatile memory device while the second processor performs the bootstrap procedure using the boot code stored in the synchronous volatile memory device.

2. The method according to claim 1, wherein a complex programmable logic device generates the reset lines of the second processor.

3. The method according to claim 2, wherein the reset lines are controlled by the first processor and handled by the complex programmable logic device.

4. The method according to claim 1, wherein a plurality of second processors are bootstrapped by loading the boot code for the plurality of second processors into a plurality of volatile memory devices, wherein each second processor is connected to a different volatile memory device.

5. The method according to claim 4, wherein the first processor provides identity to each of the plurality of second processors by posting information through the volatile memory devices containing the boot code.

6. The method according to claim 1, wherein the volatile memory device is dual port random access memory.

7. The method according to claim 1, wherein the volatile memory device is a synchronous dual port static random access memory.

8. The method according to claim 1, wherein the synchronous static random access memory has a discontinuous clock throughout the bootstrapping procedure.

9. A system for bootstrapping a plurality of slave processors from a plurality of volatile memory devices, comprising:

a master processor with an associated flash device;

a logic device for generating reset lines of the slave processors and deasserting the reset lines based on control signals from the master processor;

the volatile memory devices storing boot code for the slave processors loaded from the flash device after the master processor has been bootstrapped;

the slave processors each being connected to a separate volatile memory device, wherein when the reset lines of the slave processors are de-asserted, the slave processors bootstrap from the boot code stored in the volatile memory devices;

wherein the master processor provides identity to each of the slave processors by posting information through the volatile memory devices.

10. The system according to claim 9, wherein the logic device is a complex programmable logic device.

11. The system according to claim 10, wherein the logic device is a field programmable gate array.

12. The system according to claim 9, wherein the volatile memory devices are static random access memories.

13. The system according to claim 9, wherein the volatile memory devices are dual port random access memories.

14. The system according to claim 9, wherein the volatile memory device is a synchronous static random access memory.

15. The system according to claim 9, wherein the volatile memory devices have a discontinuous clock through out the bootstrapping procedure.

16. The system according to claim 9, further comprising:

a plurality of slave flash devices each connected to one of the slave processors, the slave flash devices having boot code for the slave processors, wherein the master processor determines whether to bootstrap the slave processors using the boot code in the slave flash devices or the boot code in the volatile memory devices.

17. The system according to claim 16, wherein the master processor sets a command register in the logic device to configure logic units for the selected bootstrap procedure.

18. A method for bootstrapping a second processor from either a flash device or a synchronous volatile memory device, comprising the steps of:

bootstrapping a master processor;

determining whether a flash bootstrap procedure or a volatile memory device bootstrap procedure has been selected for the second processor;

setting a command register in a logic device to configure logic units for the selected bootstrap procedure;

if the flash bootstrap procedure was selected;

performing bootstrap procedure from the flash device associated with the second processor;

if the volatile memory bootstrap procedure was selected;

asserting reset lines of the second processor;

loading boot code for the second processor from a flash device associated with the master processor into the volatile memory device;

de-asserting the reset lines of the second processor;

allowing a clock signal from the second processor to stabilize before providing the clock signal to the synchronous volatile memory device; and

bootstrapping the second processor from the boot code stored in the volatile memory device.

19. The method according to claim 18, wherein a complex programmable logic device generates the reset lines of the second processor.

20. The method according to claim 19, wherein the reset lines are controlled by the master processor.

21. The method according to claim 18, wherein a plurality of second processors are bootstrapped by loading the boot code for the plurality of second processors into a plurality of volatile memory devices, wherein each second processor is connected to a different volatile memory device.

22. The method according to claim 21, wherein the master processor provides identity to each of the plurality of second processors by posting information through the volatile memory devices.

23. The method according to claim 18, wherein the volatile memory device is dual port random access memory.

24. The method according to claim 18, wherein the synchronous static random access memory has a discontinuous clock through out the bootstrapping procedure.

25. A mechanism for bootstrapping a processor from a volatile memory device connected to the processor, comprising the steps of:

means for asserting reset lines of the processor;

means for loading boot code for the processor from a flash device into the volatile memory device; and

means for de-asserting the reset lines of the processor,

means for preventing the processor from reading a synchronous volatile memory device while a clock signal from the processor stabilizes after reset;

wherein the processor performs the bootstrap procedure using the boot code stored in the volatile memory device while the processor provides the clock signal to the synchronous volatile memory device.

26. The mechanism of claim 25, wherein a complex programmable logic device generates the reset lines of the processor.

27. The mechanism of claim 25, wherein at least one additional processor is bootstrapped by loading the boot code for the additional processors into additional volatile memory devices, wherein each additional processor is connected to a different additional volatile memory device.

28. The mechanism of claim 27, wherein identity to each of the processors is provided by posting information through the volatile memory devices.

29. The mechanism of claim 25, wherein the volatile memory device is dual port random access memory.

30. The mechanism of claim 29, wherein the memory control signals of the dual port static random access memory has a discontinuous clock through out the bootstrapping procedure.

31. A computing system comprising:

a nonvolatile memory device containing a master bootstrap process;

a synchronous static random access memory containing a slave bootstrap process;

a master processor in communication with the nonvolatile memory device, the master processor booting with the master bootstrap process, the master processor storing the slave bootstrap process on the synchronous static random access memory after the master processor has booted;

a slave processor in communication with the synchronous static random access memory, the slave processor providing a clock signal to the synchronous static random access memory while booting with the slave bootstrap process stored on the synchronous static random access memory.

32. A computing system comprising:

a nonvolatile memory device containing a master bootstrap process;

a synchronous random access memory containing a slave bootstrap process;

a master processor in communication with the nonvolatile memory device, the master processor booting with the master bootstrap process;

a slave processor providing a clock signal to the synchronous random access memory;

a data bus providing data communication between the synchronous random access memory and the slave processor; and

a pulldown resister network on the data bus ensuring that the slave processor receives no-op instructions over the data bus during periods of clock instability.

33. A computing system comprising:

a first volatile memory device containing a first identity;

a second volatile memory device containing a second identity;

a master processor in communication with the volatile memory devices, the master processor storing the first identity on the first volatile memory device, and the second identity on the second volatile memory device;

a first slave processor in communication with the first volatile memory device, the first slave processor obtaining the first identity from the first volatile memory; and

a second slave processor in communication with the second volatile memory device, the second slave processor obtaining the second identity from the second volatile memory.

34. The computing system of claim 33, wherein the master processor stores on each volatile memory device a slave bootstrap process, and wherein the slave processors each boot with the slave bootstrap process received from the volatile memory devices.

35. A method for bootstrapping a processor from a synchronous memory device connected to the processor, comprising the steps of:

loading the synchronous memory device with a boot code;

resetting the processor after the boot code is loaded in the synchronous memory device;

submitting no-op commands to the processor until the processor provides a reliable clock signal;

supplying the reliable clock signal to the synchronous memory device; and

loading the boot code from the synchronous memory device to the processor.

36. The method of claim 35, wherein the no-op command is created by a resister network on a data bus.

37. The method of claim 36, wherein the resister network is a pulldown network that pulls the data bus to a zero state.

38. The method of claim 35, wherein the synchronous memory device has a discontinuous clock during the loading of the boot code to the processor causing a period of clock instability.

39. The method of claim 38, wherein an instruction cache of the processor is used in conjunction with the no-op commands during the period of clock instability.

40. A computing system comprising:

a nonvolatile memory device containing a slave bootstrap process;

a synchronous volatile random access memory on which the slave bootstrap process is transferred after power up;

a data bus;

a master processor providing a control signal;

a slave processor providing a memory control signal, receiving a reset control signal, and receiving data from the synchronous volatile random access memory over the data bus, the slave processor providing a clock signal to the synchronous volatile random access memory;

a pulldown resistor network on the data bus ensuring that the slave processor receives no-op instructions over the data bus during periods of clock instability; and

a programmable logic device acting in response to the control signal from the master processor and the memory control signal from the slave processor, the programmable logic device providing a reset control signal to the slave processor and a memory control signal to the synchronous volatile random access memory.