Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data

• US 7,032,120 B2
• Filed: 07/18/2002
• Issued: 04/18/2006
• Est. Priority Date: 07/18/2002
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: El-Kik, Tony S., Niescier, Richard Joseph
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Bae, Ji H.
• Application Number:
  US10/197,719
• Publication Number:
  US 20040015732A1
• Time in Patent Office: 1,370 Days
• Field of Search: 713/300, 713/320
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled. When the device wakes up, power is first restored to the components, then the clock is turned on, and finally the outputs of the various components are released from logic level 0.

Claims

1. A computer peripheral device adapted to couple to a computer via a bus and further adapted to enter a suspend mode upon occurrence of at least one event, said device comprising:

a data processing device;

a bus interface circuit for interfacing between said data processing device and said bus;

wherein said data processing device is coupled to a power source through a switch and said bus interface circuit is coupled directly to said power source wherein said bus interface circuit retains power during a suspend mode; and

a power management circuit coupled directly to said power source, said power management circuit being a subcircuit of said bus interface circuit and being adapted to turn off said switch responsive to said event so as to remove power from said data processing device.

2. The computer peripheral device according to claim 1 wherein said peripheral device further comprises a memory, and wherein said memory is coupled to said power source through said switch.

3. The computer peripheral device according to claim 1, wherein said switch is a transistor.

4. The computer peripheral device according to claim 3 wherein said transistor comprises first and second current flow terminals coupled between said power source and said processing device and a control terminal, wherein said power management circuit controls said switch via a SUSPEND signal coupled to said control terminal of said transistor.

5. The computer peripheral device of claim 4 wherein said transistor is a FET.

6. The computer peripheral device of claim 1 further comprising a clock and wherein said power management circuit is further adapted to disable said clock in suspend mode.

7. The computer peripheral device of claim 6 wherein said power management circuit delays said disabling of said clock until after said power is removed from said processor.

8. The computer peripheral device of claim 7 wherein said power management circuit further generates a control signal, after said switch is turned off and before said clock is disabled, said control signal coupled to said bus interface circuit and said processor, that instructs them to drive their outputs to each other to a particular logic level;

and

wherein said processor and said bus interface circuit are configured to drive their outputs to each other to said particular logic level responsive to said control signal.

9. The computer peripheral device of claim 1 wherein said peripheral device couples to said power source via said bus.

10. The computer peripheral device of claim 1 wherein said peripheral device couples to a USB bus.

11. A computer peripheral device adapted to couple to a computer via a bus and further adapted to enter a suspend state responsive to at least one event, said device comprising:

at least one data processing device;

at least one memory operatively coupled to said data processing device;

a bus interface circuit for interfacing between said bus, on the one hand, and said data processing device and memory, on the other hand, wherein said data processing device is coupled to a power source through a switch and said bus interface circuit is coupled directly to said power source wherein said bus interface circuit retains power during a suspend mode; and

a power management circuit coupled directly to said power source, said power management circuit being a subcircuit of said bus interface circuit and being adapted to turn off said switch responsive to said event so as to remove power from said data processing device.

12. The computer peripheral device of claim 11 wherein said power management circuit generates a SUSPEND signal that is asserted responsive to said event and wherein said SUSPEND signal is provided to a control terminal of said switch for turning said switch off when asserted and on when unasserted.

13. The computer peripheral device of claim 12 further comprising a clock and wherein said power management circuit further comprises at least one flip-flop having an input terminal coupled to receive said SUSPEND signal and an output terminal at which a delayed version of said SUSPEND signal is generated, said delayed SUSPEND signal coupled to said clock and operative to disable said clock when asserted.

14. The computer peripheral device of claim 13 wherein said flip-flop comprises first and second flip-flops coupled in series and wherein said first flip-flop generates a first, delayed SUSPEND signal that is provided to said memory and said data processing device to cause them to drive their outputs that are coupled to said bus interface circuit to a particular logic level when said SUSPEND signal is asserted and wherein said second flip-flop generates a second, delayed SUSPEND signal that is delayed a greater period than said first, delayed SUSPEND signal, said second delayed suspend signal coupled to said clock to disable said clock when asserted.

15. The computer peripheral device of claim 14 wherein said power management circuit further comprises a counter operatively coupled to count responsive to clock pulses from said clock and wherein said second, delayed SUSPEND signal is further coupled to said counter to disable said counter when said second delayed SUSPEND signal is asserted, said counter having an output coupled to an enable input terminal of said first flip-flop so as to enable said first flip-flop after a predetermined number of clock pulses from said clock and whereby, upon exiting said SUSPEND state, said first delayed SUSPEND signal is delayed said predetermined number of clock pulses after said clock is enabled.

16. The computer peripheral device of claim 15 wherein said switch is a transistor.

17. The computer peripheral device of claim 11 wherein said peripheral device couples to said power source via said bus.

18. The computer peripheral device of claim 17 wherein said peripheral device couples to a USB bus.

19. A method of placing a computer peripheral device that is adapted to couple to a computer via a bus in a suspend state responsive to at least one event without losing configuration data, said method comprising the steps of;

(1) splitting power to said peripheral device into a first, switched power rail coupled to a processing device of said peripheral device and a second, unswitched power rail coupled to a bus interface circuit of said peripheral device wherein said bus interface circuit retains power during a suspend state; and

(2) enabling a subcircuit of said bus interface circuit to turn off said first switched power rail in response to said event.

20. The method of claim 19 wherein said peripheral device further comprises a memory, said method further comprising the step of;

(3) providing power to said memory via said first, switched power rail.

21. The method of claim 20 wherein said peripheral device further comprises a clock, said method further comprising the step of:

(4) disabling said clock after step (2).

22. The method of claim 21 further comprising the steps of:

(4) driving outputs of said processing device and said memory to said bus interface circuit to a first logic level after step (2) and before step (3); and

(5) driving outputs of said bus interface circuit to said processing device and said memory to said first logic level after step (2) and before step (3).

23. The method of claim 22 further comprising the steps of:

(6) responsive to a second event indicating that said peripheral device should exit the suspend state, turning said first, switched power rail on.

(7) responsive to said first, switched power rail being turned on, enabling said clock;

(8) responsive to said clock being enabled, releasing said outputs of said processing device, memory and bus interface circuit from said first logic state.

24. The computer peripheral device of claim 23 wherein step (8) comprises delaying step (8) a predetermined number of clock cycles after step (7).