Mask network design for scan-based integrated circuits

• US 7,032,148 B2
• Filed: 06/28/2004
• Issued: 04/18/2006
• Est. Priority Date: 07/07/2003
• Status: Expired due to Fees

• Current Assignee: Syntest Technologies Incorporated
• Original Assignee: Syntest Technologies Incorporated
• Inventors: Wen, Xiaoqing, Wang, Laung-Terng (L.-T.), Sheu, Boryau (Jack), Abdel-Hafez, Khader S., Wang, Shun-Miin (Sam)
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US10/876,784
• Publication Number:
  US 20050060625A1
• Time in Patent Office: 659 Days
• Field of Search: 714/729
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

Claims

1. A method for selectively masking off unknown (‘

x’

) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, an output-mask controller, and an output-mask network embedded on the scan data input path of second selected scan cells, each scan chain comprising multiple scan cells coupled in series;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains by using said output-mask controller to control said output-mask network to prevent said unknown (‘

x’

) captured scan data from propagating through said second selected scan cells by injecting a predetermined constant logic value, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a limiting criteria is reached.

2. The method of claim 1, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises generating a compressed stimulus, decompressing said compressed stimulus as said stimulus propagates through said pattern generators, and shifting in said stimulus to all said scan cells in said selected scan-test mode during said shift-in operation;

wherein said compressed stimulus is selectively generated internally or supplied externally from an ATE (automatic test equipment).

3. The method of claim 2, wherein each said pattern generator is selectively a broadcaster or a decompressor.

4. The method of claim 1, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises automatically generating said stimulus internally using said pattern generators in said selected self-test mode during said shift-in operation.

5. The method of claim 4, wherein each said pattern generator is selectively a pseudorandom pattern generator (PRPG) or a random pattern generator (RPG).

6. The method of claim 1, wherein said plurality of scan chains further includes selected scan chains wherein no said unknown (‘

x’

) captured scan data is present.

7. The method of claim 1, wherein said plurality of scan chains further includes selected scan chains wherein said multiple scan cells coupled in series are sorted such that no said unknown (‘

x’

) captured scan data is present after said second selected scan cells, wherein said second selected scan cells are not at the end of said selected scan chains.

8. The method of claim 1, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises using a load signal to set said output-mask controller with a predetermined state for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during a selected shift-in operation.

9. The method of claim 1, wherein said shifting out said test response or said stimulus to said pattern compactors for compaction further comprises using said output-mask controller to generate a plurality of output-mask enable signals for controlling said output-mask network for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during said shift-out operation.

10. The method of claim 9, wherein said output-mask controller further comprises using an initialize signal to prevent said plurality of output-mask enable signals from selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during a selected shift-out operation.

11. The method of claim 9, wherein said output-mask controller further comprises a sequential output controller for generating a plurality of sequential-mask signals and a combinational output controller for generating said plurality of output-mask enable signals.

12. The method of claim 11, wherein said sequential output controller in said output-mask controller further comprises a plurality of selected cell-mask controllers for generating one or more selected cell-mask enable signals, a plurality of selected chain-mask controllers for generating one or more selected chain-mask enable signals, and a plurality of selected pattern-mask controllers for generating one or more selected pattern-mask enable signals;

wherein said selected cell-mask enable signals, said selected chain-mask enable signals, and said selected pattern-mask enable signals are grouped as said plurality of sequential-mask signals.

13. The method of claim 12, wherein each said cell-mask controller in said sequential output controller is a first finite-state machine generating one or more said selected cell-mask enable signals.

14. The method of claim 13, wherein said first finite-state machine is selectively a ring counter (RC) or a first range comparator.

15. The method of claim 12, wherein each said chain-mask controller in said sequential output controller is a second finite-state machine generating one or more said selected chain-mask enable signals.

16. The method of claim 15, wherein said second finite-state machine is selectively a first shift register (SR) or a range decoder.

17. The method of claim 12, wherein each said pattern-mask controller in said sequential output controller is a third finite-state machine generating one or more said selected pattern-mask enable signals.

18. The method of claim 17, wherein said third finite-state machine is selectively a second shift register (SR) or a second range comparator.

19. The method of claim 11, wherein said combinational output controller, comprising one or more selected combinational logic networks, further accepts said plurality of sequential-mask signals as inputs for generating said plurality of output-mask enable signals for controlling said output-mask network for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during said shift-out operation.

20. The method of claim 19, wherein each said selected combinational logic network further comprises one or more first selected combinational gates;

wherein each said first selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), or inverter (INV).

21. The method of claim 1, wherein said output-mask network further comprises one or more second selected combinational gates;

wherein each said second selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, or multiplexor (MUX).

22. The method of claim 1, wherein each said pattern compactor is selectively a sequential compressor or a linear compactor;

wherein said sequential compressor further includes a multi-input signature register (MISR), and wherein said linear compactor further includes one or more third selected combinational gates;

wherein each said third selected combinational gate is selectively an Exclusive-OR (XOR) gate or Exclusive-NOR (XNOR) gate.

23. The method of claim 1, wherein each said pattern compactor is selectively an x-tolerant (unknown-tolerant) pattern compactor, wherein said x-tolerant pattern compacter is selectively an x-tolerant sequential compressor or an x-tolerant linear compactor;

wherein said x-tolerant sequential compressor further includes an x-tolerant multi-input signature register (MISR), and wherein said x-tolerant linear compactor further includes one or more fourth selected combinational gates;

wherein each said fourth selected combinational gate is selectively an Exclusive-OR (XOR) gate or Exclusive-NOR (XNOR) gate.

24. An output-mask controller for generating a plurality of output-mask enable signals for selectively masking off unknown (‘

x’

) captured scan data in first selected scan cells from propagating through the scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an output-mask network embedded on the scan data input path of second selected scan cells, each scan chain comprising multiple scan cells coupled in series;

said output-mask controller comprising;

(a) a sequential output controller for generating a plurality of sequential-mask signals; and

(b) a combinational output controller accepting said plurality of sequential-mask signals for generating said plurality of output-mask enable signals for controlling said output-mask network for selectively masking off unknown (‘

x’

) captured scan data in first selected scan cells from propagating through said scan chains.

25. The output-mask controller of claim 24, wherein said sequential output controller further comprises a load signal to load said sequential output controller with a predetermined state for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains.

26. The output-mask controller of claim 24, wherein said sequential output controller further comprises an initialize signal used to control said combinational output controller to allow all said unknown (‘

x’

) captured scan data in said first selected scan cells to propagate through said scan chains.

27. The output-mask controller of claim 24, wherein said sequential output controller further comprises a plurality of selected cell-mask controllers for generating one or more selected cell-mask enable signals, a plurality of selected chain-mask controllers for generating one or more selected chain-mask enable signals, and a plurality of selected pattern-mask controllers for generating one or more selected pattern-mask enable signals;

wherein said selected cell-mask enable signals, said selected chain-mask enable signals, and said selected pattern-mask enable signals are grouped as said plurality of sequential-mask signals.

28. The output-mask controller of claim 27, wherein each said cell-mask controller in said sequential output controller is a first finite-state machine generating one or more said selected cell-mask enable signals.

29. The output-mask controller of claim 28, wherein said first finite-state machine is selectively a ring counter (RC) or a first range comparator.

30. The output-mask controller of claim 27, wherein each said chain-mask controller in said sequential output controller is a second finite-state machine generating one or more said selected chain-mask enable signals.

31. The output-mask controller of claim 30, wherein said second finite-state machine is selectively a first shift register (SR) or a range decoder.

32. The output-mask controller of claim 27, wherein each said pattern-mask controller in said sequential output controller is a third finite-state machine generating one or more said selected pattern-mask enable signals.

33. The output-mask controller of claim 32, wherein said third finite-state machine is selectively a second shift register (SR) or a second range comparator.

34. The output-mask controller of claim 24, wherein said combinational output controller, comprising one or more selected combinational logic networks, further accepts said plurality of sequential-mask signals as inputs for generating said plurality of output-mask enable signals for controlling said output-mask network for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains.

35. The output-mask controller of claim 34, wherein each said selected combinational logic network further comprises one or more first selected combinational gates;

wherein each said first selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), or inverter (INV).

36. The output-mask controller of claim 24, wherein said output-mask network further comprises one or more second selected combinational gates;

wherein each said second selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, or multiplexor (MUX).

37. The output-mask controller of claim 24, wherein said output-mask network is not embedded on said scan data input path of said second selected scan cells of selected scan chains wherein no said unknown (‘

x’

) captured scan data is present.

38. The output-mask controller of claim 24, wherein said output-mask network is embedded on said scan data input path of said second selected scan cells of selected scan chains wherein no said unknown (‘

x’

) captured scan data is present after said second selected scan cells, wherein said second selected scan cells are not at the end of said selected scan chains.

39. A method for selectively masking off unknown (‘

x’

) captured scan data in first selected scan cells from propagating through the scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and a set/reset controller controlling selected set/reset inputs of second selected scan cells, each scan chain comprising multiple scan cells coupled in series;

said method comprising;

(a) generating and shifting in a stimulus through said pattern generators to all said scan cells in said scan-based integrated circuit during a shift-in operation;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) shifting out said test response or said stimulus to said pattern compactors for compaction by selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains by using said set/reset controller to control said selected set/reset inputs to prevent said unknown (‘

x’

) captured scan data from propagating through said second selected scan cells by injecting a predetermined constant logic value, while shifting in a new stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a limiting criteria is reached.

40. The method of claim 39, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises generating a compressed stimulus, decompressing said compressed stimulus as said stimulus through said pattern generators, and shifting in said stimulus to all said scan cells in said selected scan-test mode during said shift-in operation;

wherein said compressed stimulus is selectively generated internally or supplied externally from an ATE (automatic test equipment).

41. The method of claim 40, wherein each said pattern generator is selectively a broadcaster or a decompressor.

42. The method of claim 39, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises automatically generating said stimulus internally using said pattern generators in said selected self-test mode during said shift-in operation.

43. The method of claim 42, wherein each said pattern generator is selectively a pseudorandom pattern generator (PRPG) or a random pattern generator (RPG).

44. The method of claim 39, wherein said plurality of scan chains further includes selected scan chains wherein no said unknown (‘

x’

) captured scan data is present.

45. The method of claim 39, wherein said plurality of scan chains further includes selected scan chains wherein said multiple scan cells coupled in series are sorted such that no said unknown (‘

x’

) captured scan data is present after said second selected scan cells, wherein said second selected scan cells are not at the end of said selected scan chains.

46. The method of claim 39, wherein said generating and shifting in a stimulus through said pattern generators to all said scan cells further comprises using a load signal to set said set/reset controller with a predetermined state for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during a selected shift-in operation.

47. The method of claim 39, wherein said shifting out said test response or said stimulus to said pattern compactors for compaction further comprises using said set/reset controller to generate a plurality of set/reset signals for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during said shift-out operation.

48. The method of claim 47, wherein said set/reset controller further comprises using an initialize signal to prevent said plurality of set/reset signals from selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during a selected shift-out operation.

49. The method of claim 47, wherein said set/reset controller further comprises a sequential mask controller for generating a plurality of sequential-mask signals and a combinational set/reset controller for generating said plurality of set/reset signals.

50. The method of claim 49, wherein said sequential mask controller in said set/reset controller further comprises a plurality of selected cell-mask controllers for generating one or more selected cell-mask enable signals, a plurality of selected chain-mask controllers for generating one or more selected chain-mask enable signals, and a plurality of selected pattern-mask controllers for generating one or more selected pattern-mask enable signals;

wherein said selected cell-mask enable signals, said selected chain-mask enable signals, and said selected pattern-mask enable signals are grouped as said plurality of sequential-mask signals.

51. The method of claim 50, wherein each said cell-mask controller in said sequential mask controller is a first finite-state machine generating one or more said selected cell-mask enable signals.

52. The method of claim 51, wherein said first finite-state machine is selectively a ring counter (RC) or a first range comparator.

53. The method of claim 50, wherein each said chain-mask controller in said sequential mask controller is a second finite-state machine generating one or more said selected chain-mask enable signals.

54. The method of claim 53, wherein said second finite-state machine is selectively a first shift register (SR) or a range decoder.

55. The method of claim 50, wherein each said pattern-mask controller in said sequential mask controller is a third finite-state machine generating one or more said selected pattern-mask enable signals.

56. The method of claim 55, wherein said third finite-state machine is selectively a second shift register (SR) or a second range comparator.

57. The method of claim 49, wherein said combinational set/reset controller, comprising one or more selected combinational logic networks, further accepts said plurality of sequential-mask signals as inputs for generating said plurality of set/reset signals for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains during said shift-out operation.

58. The method of claim 57, wherein each said selected combinational logic network further comprises one or more first selected combinational gates;

wherein each said first selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), or inverter (INV).

59. The method of claim 39, wherein said set/reset controller selectively controls a selected set or a selected reset input of said second selected scan cells.

60. The method of claim 39, wherein each said pattern compactor is selectively a sequential compressor or a linear compactor;

wherein said sequential compressor further includes a multi-input signature register (MISR), and wherein said linear compactor further includes one or more second selected combinational gates;

wherein each said second selected combinational gate is selectively an Exclusive-OR (XOR) gate or Exclusive-NOR (XNOR) gate.

61. The method of claim 39, wherein each said pattern compactor is selectively an x-tolerant (unknown-tolerant) pattern compactor, wherein said x-tolerant pattern compacter is selectively an x-tolerant sequential compressor or an x-tolerant linear compactor;

wherein said x-tolerant sequential compressor further includes an x-tolerant multi-input signature register (MISR), and wherein said x-tolerant linear compactor further includes one or more third selected combinational gates;

wherein each said third selected combinational gate is selectively an Exclusive-OR (XOR) gate or Exclusive-NOR (XNOR) gate.

62. A set/reset controller for generating a plurality of set/reset signals for selectively masking off unknown (‘

x’

) captured scan data in first selected scan cells from propagating through the scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, and a plurality of pattern compactors, each scan chain comprising multiple scan cells coupled in series, said plurality of set/reset signals controlling selected set/reset inputs of second selected scan cells;

said set/reset controller comprising;

(a) a sequential mask controller for generating a plurality of sequential-mask signals; and

(b) a combinational set/reset controller accepting said plurality of sequential-mask signals for generating said plurality of set/reset signals for selectively masking off unknown (‘

x’

) captured scan data in first selected scan cells from propagating through said scan chains.

63. The set/reset controller of claim 62, wherein said sequential mask controller further comprises a load signal to load said sequential mask controller with a predetermined state for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains.

64. The set/reset controller of claim 62, wherein said sequential mask controller further comprises an initialize signal used to control said combinational set/reset controller to allow all said unknown (‘

x’

) captured scan data in said first selected scan cells to propagate through said scan chains.

65. The set/reset controller of claim 62, wherein said sequential mask controller further comprises a plurality of selected cell-mask controllers for generating one or more selected cell-mask enable signals, a plurality of selected chain-mask controllers for generating one or more selected chain-mask enable signals, and a plurality of selected pattern-mask controllers for generating one or more selected pattern-mask enable signals;

wherein said selected cell-mask enable signals, said selected chain-mask enable signals, and said selected pattern-mask enable signals are grouped as said plurality of sequential-mask signals.

66. The set/reset controller of claim 65, wherein each said cell-mask controller in said sequential mask controller is a first finite-state machine generating one or more said selected cell-mask enable signals.

67. The set/reset controller of claim 66, wherein said first finite-state machine is selectively a ring counter (RC) or a first range comparator.

68. The set/reset controller of claim 65, wherein each said chain-mask controller in said sequential mask controller is a second finite-state machine generating one or more said selected chain-mask enable signals.

69. The set/reset controller of claim 68, wherein said second finite-state machine is selectively a first shift register (SR) or a range decoder.

70. The set/reset controller of claim 65, wherein each said pattern-mask controller in said sequential mask controller is a third finite-state machine generating one or more said selected pattern-mask enable signals.

71. The set/reset controller of claim 70, wherein said third finite-state machine is selectively a second shift register (SR) or a second range comparator.

72. The set/reset controller of claim 62, wherein said combinational set/reset controller, comprising one or more selected combinational logic networks, further accepts said plurality of sequential-mask signals as inputs for generating said plurality of set/reset signals for selectively masking off said unknown (‘

x’

) captured scan data in said first selected scan cells from propagating through said scan chains.

73. The set/reset controller of claim 72, wherein each said selected combinational logic network further comprises one or more first selected combinational gates;

wherein each said first selected combinational gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), or inverter (INV).

74. The set/reset controller of claim 62, wherein said plurality of set/reset signals selectively control a selected set or a selected reset input of said second selected scan cells.

75. The set/reset controller of claim 62, wherein said plurality of set/reset signals do not control said selected set/reset inputs of second selected scan cells of selected scan chains wherein no said unknown (‘

x’

) captured scan data is present.

76. The set/reset controller of claim 62, wherein said plurality of set/reset signals control said selected set/reset inputs of said second selected scan cells of selected scan chains wherein no said unknown (‘

x’

) captured scan data is present after said second selected scan cells, wherein said second selected scan cells are not at the end of said selected scan chains.