Differentially mis-aligned contacts in flash arrays to calibrate failure modes

• US 7,032,193 B1
• Filed: 12/17/2002
• Issued: 04/18/2006
• Est. Priority Date: 09/30/2002
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hill, W. Eugene
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US10/320,910
• Time in Patent Office: 1,218 Days
• Field of Search: 716 4- 5, 716/19, 438 14- 15, 438/18, 438/200, 438/257, 438/657, 702/42, 702/57, 702/85, 702/108, 324/765, 714/42, 714/718
• US Class Current: 438/18
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method and apparatus for calibrating failures in semiconductor memory devices due to contact mask misalignment includes: providing a plurality of semiconductor memory devices on a die; providing a contact mask with a plurality of known offsets; creating a plurality of contacts on the die using the contact mask; determining which devices on the die fail; and creating a pass/fail map for the devices. The pass/fail map can be used to determine the range of allowed misalignment and the amount of misalignment, providing a better understanding of how contact mask misalignment affects the yield and reliability of the memory devices. The pass/fail map may also be used for comparison with a pass/fail map created after the arrays have been subjected to a known stress.

Claims

1. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:

(a) providing a first plurality of semiconductor memory devices on a first die;

(b) providing a contact mask with a plurality of known offsets;

(c) creating a first plurality of contacts on the first die using the contact mask;

(d) determining which of the first plurality of semiconductor memory devices on the first die fail; and

(e) creating a first pass/fail map for the first plurality of semiconductor memory devices.

2. The method of claim 1, wherein the determining step (d) comprises:

(d1) measuring a parameter for each of the first plurality of semiconductor memory devices on the first die.

3. The method of claim 2, wherein the parameter comprises one or more of the group consisting of:

charge leakage;

charge loss; and

bit failure.

4. The method of claim 1, further comprising:

(f) determining a range of contact mask misalignment allowed for passing semiconductor memory devices on the first die using the first pass/fail map.

5. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:

(a) providing a plurality of semiconductor memory devices on a die;

(b) providing a contact mask with a plurality of known offsets;

(c) creating a plurality of contacts on the die using the contact mask;

(d) determining which of the plurality of semiconductor memory devices on the die fail;

(e) creating a first pass/fail map for the plurality of semiconductor memory devices; and

(f) determining a range of contact mask misalignment allowed for passing semiconductor memory devices using the first pass/fail map.

6. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:

(a) providing a plurality of semiconductor memory devices on a die;

(b) providing a contact mask with a plurality of known offsets;

(c) creating a plurality of contacts on the die using the contact mask;

(d) determining which of the plurality of semiconductor memory devices on the die fail;

(e) creating a first pass/fail map for the plurality of semiconductor memory devices;

(f) subjecting the plurality of semiconductor memory devices on the die to a known stress;

(g) creating a second pass/fail map for the devices after subjecting the plurality of semiconductor memory devices to the known stress; and

(h) comparing the second pass/fail map with the first pass/fail map.

7. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:

(a) providing a first plurality of semiconductor memory devices on a first die;

(b) providing a contact mask with a plurality of known offsets;

(c) creating a first plurality of contacts on the first die using the contact mask;

(d) determining which of the first plurality of semiconductor memory devices on the first die fail;

(e) creating a first pass/fail map for the first plurality of semiconductor memory devices;

(f) creating a second plurality of contacts on a second die using the contact mask;

(g) determining which of a second plurality of semiconductor memory devices on the second die fail;

(h) creating a second pass/fail map for the second plurality of semiconductor memory devices on the second die; and

(i) comparing the second pass/fail map with the first pass/fail map to determine an amount of misalignment of the contact mask.