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Method and apparatus for decomposing a region of an integrated circuit layout

  • US 7,032,201 B1
  • Filed: 08/28/2002
  • Issued: 04/18/2006
  • Est. Priority Date: 01/22/2002
  • Status: Expired due to Fees
First Claim
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1. A method of decomposing a region of an integrated circuit (“

  • IC”

    ) layout, the region containing a plurality of routable elements, the method comprising;

    a) based on the routable elements, defining a plurality of nodes in the region, wherein defining the nodes comprises defining nodes at a boundary of the elements;

    b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.

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