Method and apparatus for decomposing a region of an integrated circuit layout

• US 7,032,201 B1
• Filed: 08/28/2002
• Issued: 04/18/2006
• Est. Priority Date: 01/22/2002
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Caldwell, Andrew
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US10/230,503
• Time in Patent Office: 1,329 Days
• Field of Search: 716/7, 716/13, 716/14, 345/420, 345/423, 700/98, 703/1, 703/2
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.

Claims

1. A method of decomposing a region of an integrated circuit (“

IC”

) layout, the region containing a plurality of routable elements, the method comprising;

a) based on the routable elements, defining a plurality of nodes in the region, wherein defining the nodes comprises defining nodes at a boundary of the elements;

b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.

2. The method of claim 1, wherein at least some routable elements have vertices and edges between the vertices, wherein defining nodes at the boundary of the routable elements further comprises defining nodes at vertices of the routable elements.

3. The method of claim 2, wherein defining nodes at the boundary of the routable elements further comprises defining nodes along edges of the routable elements.

4. A method of decomposing a region of an integrated circuit(“

IC”

) layout, the region containing a plurality of routable elements and a set of obstacles, the method comprising;

a) defining a plurality of nodes based on the obstacles, wherein defining the nodes comprises defining nodes at a boundary of the obstacles;

b) based on the routable elements, defining a plurality of nodes in the region, wherein defining the nodes in the region comprises defining nodes at a boundary of the routable elements;

c) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.

5. A computer readable medium that stores a computer program for decomposing a region of an integrated circuit (“

IC”

) layout, the region containing a plurality of routable elements, the computer program comprising instructions for;

a) based on the routable elements, defining a plurality of nodes in the region, wherein the instructions for defining the nodes comprises instructions for defining nodes at a boundary of the routable elements;

b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.

6. The computer readable medium of claim 5, wherein at least some routable elements have vertices and edges between the vertices, wherein the instructions for defining nodes at the boundary of the routable elements further comprises instructions for defining nodes at vertices of the routable elements.

7. The computer readable medium of claim 6, wherein the instructions for defining nodes at the boundary of the routable elements further comprises instructions for defining nodes along edges of the routable elements.

8. A computer readable medium of that stores a computer program for decomposing a region of an integrated circuit (“

IC”

) layout, wherein the region contains a set of obstacles, the computer program comprising instructions for;

a) defining a plurality of nodes based on the obstacles;

wherein the instructions for defining the nodes comprises instructions for defining nodes at a boundary of the routable elements;

b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.

9. A method of decomposing a region of an integrated circuit (“

IC”

) layout, the region containing a plurality of obstacles, the method comprising;

a) based on the obstacles, defining a plurality of nodes in the region;

wherein defining the nodes comprises defining nodes at a boundary of the obstacles;

b) defining triangles in the region based on the nodes, wherein the triangles are for use in defining routes in the region.