Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby

• US 7,033,664 B2
• Filed: 10/22/2002
• Issued: 04/25/2006
• Est. Priority Date: 10/22/2002
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Katraro, Reuven, Zilber, Gil, Teomim, Doron
• Primary Examiner(s): Watkins, III, William P.
• Application Number:
  US10/277,498
• Publication Number:
  US 20040076797A1
• Time in Patent Office: 1,281 Days
• Field of Search: 428/166, 428/137, 428/131, 428/68, 428/69, 428/76, 428/178, 257/434, 257/730, 257/433, 257/431, 257/432, 257/414, 257/678, 257/687, 257/253, 257/684, 438/49, 438/64, 438/116, 438/125
• US Class Current: 428/131
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10T 428/23 Sheet including cover or casing
• CPC Class Codes: Y10T 428/231 Filled with gas other than air; or under vacuum
• CPC Class Codes: Y10T 428/239 Complete cover or casing
• CPC Class Codes: Y10T 428/24273 including aperture
• CPC Class Codes: Y10T 428/24322 Composite web or sheet
• CPC Class Codes: Y10T 428/24562 Interlaminar spaces
• CPC Class Codes: Y10T 428/24661 Forming, or cooperating to form cells
• CPC Class Codes: Y10T 428/24744 Longitudinal or transverse tubular cavity or cell

Abstract

A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.

Claims

1. A crystalline substrate based device comprising:

a crystalline substrate having formed thereon a microstructure;

at least one chip scale packaging layer which is formed over said microstructure;

a spacer element, disposed between said at least one chip scale packaging layer and said crystalline substrate, said crystalline substrate, said at least one chip scale packaging layer and said spacer element defining at least one gap between said crystalline substrate and said at least one chip scale packaging layer, said crystalline substrate, said microstructure and said at least one chip scale packaging layer forming a chip scale package having two major faces and a plurality of edge faces extending along the periphery of and between said major faces;

at least one opening in said spacer element along one of said plurality of edge faces of said chip scale package communicating with said at least one gap; and

at least one electrical contact formed on said chip scale package.

2. A crystalline substrate based device according to claim 1 and wherein said at least one chip scale packaging layer is attached to said crystalline substrate using an adhesive.

3. A crystalline substrate based device according to claim 1 and wherein said at least one chip scale packaging layer is attached to said crystalline substrate using a soldering material.

4. A crystalline substrate based device according to claim 1 and wherein said at least one chip scale packaging layer is attached to said crystalline substrate using intermetalic layer.

5. A crystalline substrate based device according to claim 2 and wherein said adhesive comprises Thermoplastic materials.

6. A crystalline substrate based device according to claim 2 and wherein said adhesive comprises Thermosetting materials.

7. A crystalline substrate based device according to claim 2 and wherein said adhesive comprises epoxy.

8. A crystalline substrate based device according to claim 1 and wherein said crystalline substrate comprises silicon.

9. A crystalline substrate based device according to claim 1 and wherein said crystalline substrate comprises lithium niobate.

10. A crystalline substrate based device according to claim 1 and wherein said crystalline substrate comprises lithium tantalite.

11. A crystalline substrate based device according to claim 1 and wherein said crystalline substrate comprises quartz.

12. A crystalline substrate based device according to claim 1 and wherein said crystalline substrate comprises GaAs.

13. A crystalline substrate based device according to claim 1 and wherein said at least one chip scale packaging layer is at least partially transparent.

14. A crystalline substrate based device according to claim 13 and wherein said at least one chip scale packaging layer is transparent at least in the spectral range of 100 nm–

20 micron.

15. A crystalline substrate based device according to claim 1 and wherein said at least one gap comprises a plurality of gaps.

16. A crystalline substrate based device according to claim 1 and wherein said microstructure comprises a micromechanical structure.

17. A crystalline substrate based device according to claim 1 and wherein said microstructure comprises a microelectronic structure.

18. A crystalline substrate based device according to claim 1 and wherein said microstructure comprises an optoelectronic structure.

19. A packaged crystalline substrate comprising:

a substrate having formed thereon a microstructure;

at least one chip scale package which is attached to said substrate over said microstructure, said at least one chip scale package having two major faces and a plurality of edge faces extending along the periphery of and between said major faces, and including a spacer element disposed between said at least one chip scale package and said substrate, said substrate, said at least one chip scale package and said spacer element defining at least one gap between said substrate and said at least one chip scale package, said at least one chip scale package containing at least one opening along at least one of said plurality of edge faces of said at least one chip scale package communicating with said at least one gap; and

at least one electrical contact formed on said at least one chip scale package.

20. A packaged crystalline substrate according to claim 19 and wherein said at least one chip scale package is attached to said substrate using an adhesive.

21. A packaged crystalline substrate according to claim 19 and wherein said at least one chip scale package is attached to said substrate using a soldering material.

22. A packaged crystalline substrate according to claim 19 and wherein said at least one chip scale package is attached to said substrate using intermetalic layer.

23. A packaged crystalline substrate based device according to claim 20 and wherein said adhesive comprises Thermosetting materials.

24. A packaged crystalline substrate based device according to claim 20 and wherein said adhesive comprises Thermoplastic materials.

25. A packaged crystalline substrate based device according to claim 20 and wherein said adhesive comprises epoxy.

26. A packaged crystalline substrate according to claim 19 and wherein said substrate comprises silicon.

27. A packaged crystalline substrate according to claim 19 and wherein said substrate comprises lithium niobate.

28. A packaged crystalline substrate according to claim 19 and wherein said substrate comprises lithium tantalite.

29. A packaged crystalline substrate according to claim 19 and wherein said substrate comprises quartz.

30. A packaged crystalline substrate according to claim 19 and wherein said substrate comprises GaAs.

31. A packaged crystalline substrate according to claim 19 and wherein said at least one chip scale package is at least partially transparent.

32. A packaged crystalline substrate according to claim 19 and wherein said at least one gap comprises a plurality of gaps.

33. A packaged crystalline substrate according to claim 19 and wherein said microstructure comprises a micromechanical structure.

34. A packaged crystalline substrate according to claim 19 and wherein said microstructure comprises a microelectronic structure.

35. A packaged crystalline substrate according to claim 19 and wherein said microstructure comprises an optoelectronic structure.

36. A packaged crystalline substrate according to claim 19 and wherein said at least one gap is filled with fluid.

37. A crystalline substrate based device according to claim 31 and wherein said at least one chip scale packaging layer is transparent at least in the spectral range of 100 nm–

20 micron.